-
1
-
-
29044440093
-
FinFET - A self-aligned double-gate MOSFET scalable to 20 nm
-
Dec.
-
D. Hisamoto, W.-C. Lee, J. Kedzierski, J. Bokor, and C. Hu, "FinFET - A self-aligned double-gate MOSFET scalable to 20 nm," IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2320-2325, Dec. 2000.
-
(2000)
IEEE Trans. Electron Devices
, vol.47
, Issue.12
, pp. 2320-2325
-
-
Hisamoto, D.1
Lee, W.-C.2
Kedzierski, J.3
Bokor, J.4
Hu, C.5
-
2
-
-
0032655915
-
Impact of highgate dielectrics and metal gate electrodes on sub-100 nm MOSFETs
-
Jul.
-
B. Cheng, M. Cao, R. Rao, A. Inani, P. Vande Voorde, W M. Greene, J. M. C. Stork, Z. Yu, S. R M. Zeitzoff, and J. C. S. Woo, "Impact of highgate dielectrics and metal gate electrodes on sub-100 nm MOSFETs," IEEE Trans. Electron Devices, vol. 46, no. 7, pp. 1537-1543, Jul. 1999.
-
(1999)
IEEE Trans. Electron Devices
, vol.46
, Issue.7
, pp. 1537-1543
-
-
Cheng, B.1
Cao, M.2
Rao, R.3
Inani, A.4
Vande Voorde, P.5
Greene, W.M.6
Stork, J.M.C.7
Yu, Z.8
Zeitzoff, S.R.M.9
Woo, J.C.S.10
-
3
-
-
0036564323
-
The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performance
-
May
-
N. R. Mohapatra, M. P. Desai, S. G. Narendra, and V. R. Rao, "The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performance," IEEE Trans. Electron Devices, vol. 49, no. 5, pp. 826-831, May 2002.
-
(2002)
IEEE Trans. Electron Devices
, vol.49
, Issue.5
, pp. 826-831
-
-
Mohapatra, N.R.1
Desai, M.P.2
Narendra, S.G.3
Rao, V.R.4
-
4
-
-
3943110263
-
A functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm fin widths applicable for the 45-nm CMOS node
-
Aug.
-
N. Collaert, A. Dixit, M. Goodwin, K. G. Anil, R. Rooyackers, B. Degroote, L. H. A. Leunissen, A. Veloso, R. Jonckheere, K. De Meyer, M. Jurczak, and S. Biesemans, "A functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm fin widths applicable for the 45-nm CMOS node," IEEE Electron Device Lett., vol. 25, no. 8, pp. 568-570, Aug. 2004.
-
(2004)
IEEE Electron Device Lett.
, vol.25
, Issue.8
, pp. 568-570
-
-
Collaert, N.1
Dixit, A.2
Goodwin, M.3
Anil, K.G.4
Rooyackers, R.5
Degroote, B.6
Leunissen, L.H.A.7
Veloso, A.8
Jonckheere, R.9
De Meyer, K.10
Jurczak, M.11
Biesemans, S.12
-
5
-
-
13344270339
-
Modeling and optimization of fringe capacitance of nanoscale DGMOS devices
-
Feb.
-
A. Bansal, B. C. Paul, and K. Roy, "Modeling and optimization of fringe capacitance of nanoscale DGMOS devices," IEEE Trans. Electron Devices, vol. 52, no. 2, pp. 255-262, Feb. 2005.
-
(2005)
IEEE Trans. Electron Devices
, vol.52
, Issue.2
, pp. 255-262
-
-
Bansal, A.1
Paul, B.C.2
Roy, K.3
-
6
-
-
33644989732
-
Performance assessment of nanoscale double- and triple-gate FinFETs
-
Apr.
-
A. Kranti and G. A. Armstrong, "Performance assessment of nanoscale double- and triple-gate FinFETs," Semicond Sci. Technol., vol. 21, no. 4, pp. 409-421, Apr. 2006.
-
(2006)
Semicond Sci. Technol.
, vol.21
, Issue.4
, pp. 409-421
-
-
Kranti, A.1
Armstrong, G.A.2
-
7
-
-
32044450519
-
Simulation of nanoscale MOSFETs using modified drift-diffusion and hydrodynamic models and comparison with monte carlo results
-
Feb.
-
R. Granzner, V. M. Polyakov, F. Schwierz, M. Kittler, R. J. Luyken, W Rosner, and M. Stadele, "Simulation of nanoscale MOSFETs using modified drift-diffusion and hydrodynamic models and comparison with Monte Carlo results," Microelectron. Eng., vol. 83, no. 2, pp. 241-246, Feb. 2006.
-
(2006)
Microelectron. Eng.
, vol.83
, Issue.2
, pp. 241-246
-
-
Granzner, R.1
Polyakov, V.M.2
Schwierz, F.3
Kittler, M.4
Luyken, R.J.5
Rosner, W.6
Stadele, M.7
-
8
-
-
33646023723
-
Analog/RF performance of multiple gate SOI devices: Wideband simulations and characterization
-
May
-
J.-P. Raskin, T. M. Chung, V. Kilchytska, D. Lederer, and D. Flandre, "Analog/RF performance of multiple gate SOI devices: Wideband simulations and characterization," IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1088-1095, May 2006.
-
(2006)
IEEE Trans. Electron Devices
, vol.53
, Issue.5
, pp. 1088-1095
-
-
Raskin, J.-P.1
Chung, T.M.2
Kilchytska, V.3
Lederer, D.4
Flandre, D.5
-
9
-
-
26244452166
-
Bulk inversion in FinFETs and implied insights on effective gate width
-
Sep.
-
S.-H. Kim, J. G. Fossum, and V. P. Trivedi, "Bulk inversion in FinFETs and implied insights on effective gate width," IEEE Trans. Electron Devices, vol. 52, no. 9, pp. 1993-1997, Sep. 2005.
-
(2005)
IEEE Trans. Electron Devices
, vol.52
, Issue.9
, pp. 1993-1997
-
-
Kim, S.-H.1
Fossum, J.G.2
Trivedi, V.P.3
-
10
-
-
33744739412
-
Parasitic S/D resistance reduction in N-channel SOI MuGFETs with 15 nm wide fins
-
A. Dixit et al., "Parasitic S/D resistance reduction in N-channel SOI MuGFETs with 15 nm wide fins," in Proc. IEEE SOI Conf., 2005, pp. 226-228.
-
(2005)
Proc. IEEE SOI Conf.
, pp. 226-228
-
-
Dixit, A.1
-
11
-
-
21044449128
-
Analysis of the parasitic S/D resistance in multiple-gate FETs
-
Jun.
-
A. Dixit, K. G. Anil, N. Collaert, and K. De Mayer, "Analysis of the parasitic S/D resistance in multiple-gate FETs," IEEE Trans. Electron Devices, vol. 52, no. 6, pp. 1132-1148, Jun. 2005.
-
(2005)
IEEE Trans. Electron Devices
, vol.52
, Issue.6
, pp. 1132-1148
-
-
Dixit, A.1
Anil, K.G.2
Collaert, N.3
De Mayer, K.4
|