Silicon-based dynamic synapse with depressing response

IEEE Transactions on Neural Networks and Learning Systems

Volumn 23, Issue 10, 2012, Pages 1513-1525

  Dowrick, Thomas ^a   Hall, Steve ^a   McDaid, Liam J ^b  

^a UNIVERSITY OF LIVERPOOL   (United Kingdom)

^b UNIVERSITY OF ULSTER   (United Kingdom)

Author keywords

Depressing synapses; neural network hardware; neuromorphic engineering; spike timing dependent plasticity (STDP)

Indexed keywords

COMPLEMENTARY METAL OXIDE SEMICONDUCTORS; DEPRESSING SYNAPSIS; METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR; NEURAL NETWORK HARDWARE; NEUROMORPHIC ENGINEERING; POST-SYNAPTIC POTENTIALS; SIMPLE CURRENT MIRRORS; SPIKE-TIMING-DEPENDENT PLASTICITY;

CHARGE TRANSFER; HARDWARE; MOSFET DEVICES; NEURAL NETWORKS;

NEURONS;

ANIMAL; BIOLOGICAL MODEL; BIOMIMETICS; DEVICE FAILURE ANALYSIS; DEVICES; EQUIPMENT DESIGN; HUMAN; NERVE CELL; NERVE CELL INHIBITION; PHYSIOLOGY; SEMICONDUCTOR; SYNAPSE; SYNAPTIC POTENTIAL; SYNAPTIC TRANSMISSION;

ANIMALS; BIOMIMETICS; EQUIPMENT DESIGN; EQUIPMENT FAILURE ANALYSIS; HUMANS; MODELS, NEUROLOGICAL; NEURAL INHIBITION; NEURONS; SYNAPSES; SYNAPTIC POTENTIALS; SYNAPTIC TRANSMISSION; TRANSISTORS, ELECTRONIC;

EID: 84875112887     PISSN: 2162237X     EISSN: 21622388     Source Type: Journal    
DOI: 10.1109/TNNLS.2012.2211035     Document Type: Review

References (49)

1. M. A. Arbib, The Handbook of Brain Theory and Neural Networks: Cambridge, Mass. Cambridge, MA: MIT Press, 1995.
2. K. J. Cios and D. M. Sala, "Advances in applications of spiking neuron networks," Proc. SPIE, vol. 4055, pp. 324-336, Mar. 2000.
3. A. Delorme, J. Gautrais, R. van Rullen, and S. Thorpe, "SpikeNET: A simulator for modeling large networks of integrate and fire neurons," Neurocomputing, vols. 26-27, pp. 989-996, Jun. 1999.
4. M. Migliore, C. Cannia, W. W. Lytton, H. Markram, and M. L. Hines, "Parallel network simulations with NEURON," J. Comput. Neurosci., vol. 21, no. 2, pp. 119-129, 2006.
5. R. Brette, M. Rudolph, T. Carnevale, M. Hines, D. Beeman, J. M. Bower, M. Diesmann, A. Morrison, P. H. Goodman, F. C. Harris, M. Zirpe, T. Natschlager, D. Pecevski, B. Ermentrout, M. Djurfeldt, A. Lansner, O. Rochel, T. Vieville, E. Muller, A. P. Davison, S. Boustani, and A. Destexhe, "Simulation of networks of spiking neurons: A review of tools and strategies," J. Comput. Neurosci., vol. 23, no. 3, pp. 349-398, 2007.
6. A. F. Murray and R. Woodburn, "The prospects for analogue neural VLSI," Int. J. Neural Syst., vol. 8, no. 5, pp. 559-579, 1997.
7. S.-C. Liu, J. Kramer, G. Indiveri, T. Delbruck, T. Burg, and R. Douglas, "Orientation-selective aVLSI spiking neurons," Neural Netw., vol. 14, nos. 6-7, pp. 629-643, 2001.
8. C. Diorio, D. Hsu, and M. Figueroa, "Adaptive CMOS: From biological inspiration to systems-on-a-chip," Proc. IEEE, vol. 90, no. 3, pp. 345-357, Mar. 2002.
9. W. Zhou, D. Jin, and Z. Li, "Review of the research on realization of analog neural cells," Guti Dianzixue Yanjiu Yu Jinzhan/Res. Progress Solid State Electron., vol. 22, pp. 268-279, 2002.
10. B. Katz, Nerve, Muscle and Synapse. New York: McGraw-Hill, 1966.
11. M. V. Tsodyks and H. Markram, "The neural code between neocortical pyramidal neurons depends on neurotransmitter release probability," Proc. Nat. Academy Sci. United States Amer., vol. 94, pp. 719-723, Jan. 1997.
12. M. Tsodyks, K. Pawelzik, and H. Markram, "Neural networks with dynamic synapse," Neural Comput., vol. 10, no. 4, pp. 821-885, 1998.
13. L. Pantic, J. J. Torres, and H. J. Kappen, "On the role of dynamical synapses in coincidence detection," Neurocomputing, vols. 38-40, pp. 285-291, Jun. 2001.
14. G. Indiveri, E. Chicca, and R. Douglas, "A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity," IEEE Trans. Neural Netw., vol. 17, no. 1, pp. 211-221, Jan. 2006.
15. J. H. B. Wijekoon and P. Dudek, "A simple analogue VLSI circuit of a cortical neuron," in Proc. IEEE Int. Conf. Electron. Circuits Syst., Dec. 2006, pp. 1344-1347.
16. Y. L. Wong, X. Peng, and P. Abshire, "Ultralow spike rate silicon neuron," in Proc. IEEE Biomed. Circuits Syst. Conf., Nov. 2007, pp. 95-98.
17. S. R. Schultz and M. A. Jabri, "Analogue VLSI 'integrate-and-fire' neuron with frequency adaptation," Electron. Lett., vol. 31, no. 16, pp. 1357-1358, Aug. 1995.
18. K. A. Boahen, "Pixel-parallel adaptive amplification, filtering, and quantization," Analog Integr. Circuits Signal Process., vol. 13, nos. 1-2, pp. 53-68, 1997.
19. E. Chicca, G. Indiveri, and R. Douglas, "An adaptive silicon synapse," in Proc. Circuits Syst. Int. Symp., May 2003, pp. 81-84.
20. J. B. Lont and W. Guggenbuhl, "Analog CMOS implementation of a multilayer perceptron with nonlinear synapses," IEEE Trans. Neural Netw., vol. 3, no. 3, pp. 457-465, May 1992.
21. E. Lazaridis, E. M. Drakakis, and M. Barahona, "A biomimetic CMOS synapse," in Proc. IEEE Int. Circuits Syst. Symp., May 2006, pp. 21-24.
22. H. C. Card, C. R. Schneider, and W. R. Moore, "Hebbian plasticity in MOS synapses," IEE Proc. Radar Signal Process., vol. 138, no. 1, pp. 13-16, Feb. 1991.
23. L. Shih-Chii and R. Douglas, "Temporal coding in a silicon network of integrate-and-fire neurons," IEEE Trans. Neural Netw., vol. 15, no. 5, pp. 1305-1314, Sep. 2004.
24. E. Chicca, D. Badoni, V. Dante, M. D'Andreagiovanni, G. Salina, L. Carota, S. Fusi, and P. Del Giudice, "A VLSI recurrent network of integrate-and-fire neurons connected by plastic synapses with long-term memory," IEEE Trans. Neural Netw., vol. 14, no. 5, pp. 1297-1307, Sep. 2003.
25. S. Mitra, S. Fusi, and G. Indiveri, "A VLSI spike-driven dynamic synapse which learns only when necessary," in Proc. IEEE Int. Symp. Circuits Syst., May 2006, pp. 21-24.
26. C. Gordon, A. Preyer, K. Babalola, R. J. Butera, and P. Hasler, "An artificial synapse for interfacing to biological neurons," in Proc. IEEE Int. Symp. Circuits Syst., May 2006, pp. 1124-1126.
27. C. Diorio, "A p-channel MOS synapse transistor with self-convergent memory writes," IEEE Trans. Electron Dev., vol. 47, no. 2, pp. 464-472, Feb. 2000.
28. C. Diorio, P. Hasler, A. Minch, and C. A. Mead, "A single-transistor silicon synapse," IEEE Trans. Electron Dev., vol. 43, no. 11, pp. 1972-1980, Nov. 1996.
29. A. Afifi, A. Ayatollahi, and F. Raissi, "Implementation of biologically plausible spiking neural network models on the memristor crossbarbased CMOS/nano circuits," in Proc. Eur. Conf. Circuit Theory Des. Conf., Aug. 2009, pp. 563-566.
30. C. Rasche and R. H. R. Hahnloser, "Silicon synaptic depression," Biolog. Cybern., vol. 84, no. 1, pp. 57-62, 2001.
31. M. Boegerhausen, P. Suter, and S. C. Liu, "Modeling short-term synaptic depression in silicon," Neural Comput., vol. 15, no. 2, p. 331-348, 2003.
32. C. Diorio, "A floating-gate MOS learning array with locally computed weight updates," IEEE Trans. Electron Dev., vol. 44, no. 12, pp. 2281-2289, Dec. 1997.
33. G. Serrano, P. D. Smith, H. J. Lo, R. Chawla, T. S. Hall, C. M. Twigg, and P. Hasler, "Automatic rapid programming of large arrays of floatinggate elements," in Proc. Circuits Syst. Int. Symp., May 2004, pp. 373-376.
34. J. Partzsch and R. Schuffny, "Analyzing the scaling of connectivity in neuromorphic hardware and in models of neural networks," IEEE Trans. Neural Netw., vol. 22, no. 6, pp. 919-935, Jun. 2011.
35. K. Minkovich, N. Srinivasa, J. M. Cruz-Albrecht, Y. Cho, and A. Nogin, "Programming time-multiplexed reconfigurable hardware using a scalable neuromorphic compiler," IEEE Trans. Neural Netw., vol. 23, no. 6, pp. 889-901, Jun. 2012.
36. S. A. Bamford, A. F. Murray, and D. J. Willshaw, "Large developing receptive fields using a distributed and locally reprogrammable addressevent receiver," IEEE Trans. Neural Netw., vol. 21, no. 2, pp. 286-304, Feb. 2010.
37. A. D. Rast, Y. Shufan, M. Khan, and S. B. Furber, "Virtual synaptic interconnect using an asynchronous network-on-chip," in Proc. IEEE Int. Neural Netw. Joint Conf., Jun. 2008, pp. 2727-2734.
38. X. Jin, A. Rast, F. Galluppi, M. Khan, and S. Furber, "Implementing learning on the SpiNNaker universal neural chip multiprocessor," in Proc. 16th Int. Conf. Neural Inform. Process., 2009, pp. 425-432.
39. Q. Zou, Y. Bornat, S. Saighi, J. Tomas, S. Renaud, and A. Destexhe, "Analog-digital simulations of full conductance-based networks of spiking neurons with spike timing dependent plasticity," Netw. Comput. Neural Syst., vol. 17, no. 3, pp. 211-233, 2006.
40. J. Tomas, Y. Bornat, S. Saighi, T. Lacvi, and S. Renaud, "Design of a modular and mixed neuromimetic ASIC," in Proc. IEEE Int. Conf. Electron. Circuits Syst. Nice, Dec. 2006, pp. 946-949.
41. S. Renaud, J. Tomas, Y. Bornat, A. Daouzli, and S. Saighi, "Neuromimetic ICs with analog cores: An alternative for simulating spiking neural networks," in Proc. IEEE Int. Symp. Circuits Syst., May 2007, pp. 3355-3358.
42. S. C. Liu and R. Douglas, "Temporal coding in a silicon network of integrate-and-fire neurons," IEEE Trans. Neural Netw., vol. 15, no. 5, pp. 1305-1314, Sep. 2004.
43. C. Bartolozzi and G. Indiverdi, "Synaptic dynamics in analog VLSI," Neural Comput., vol. 19, no. 10, pp. 2581-2603, 2007.
44. H. Markram, D. Pikus, A. Gupta, and M. Tsodyks, "Potential for multiple mechanisms, phenomena and algorithms for synaptic plasticity at single synapses," Neuropharmacology, vol. 37, nos. 4-5, pp. 489-500, 1998.
45. M. Noack, C. Mayr, J. Partzsch, and R. Schuffy, "Synapse dynamics in CMOS derived from a model of neurotransmitter release," in Proc. 20th Eur. Cof. Circuit Theory Des., Aug. 2011, pp. 198-201.
46. A. Ghani, L. McDaid, A. Belatreche, P. Kelly, S. Hall, T. Dowrick, S. Huang, J. Marsland, and A. Smith, "Evaluating the training dynamics of a CMOS based synapse," in Proc. IEEE Int. Joint Conf., Jul. 2011, pp. 1162-1168.
47. J. Harkin, F. Morgan, L. McDaid, S. Hall, B. McGinley, and S. Cawley, "A reconfigurable and biologically inspired paradigm for computation using networks-on-chip and spiking neural networks," Int. J. Reconfigurable Comput., vol. 2009, pp. 1-13, Jan. 2009.
48. W. E. G. Gerald, M. Edelman, and W. M. Cowan, Synaptic Function. New York: Wiley, 1987.
49. J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital integrated circuits: A design perspective, 2nd ed. Englewood Cliffs, NJ: Prentice-Hall, 2002.