Automatic rapid programming of large arrays of floating-gate elements

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2004, Pages

  Serrano, G ^a   Smith, P D ^a   Lo, H J ^a   Chawla, R ^a   Hall, T S ^a   Twigg, C M ^a   Hasler, P ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC RAPID PROGRAMMING; FLOATING GATE ELEMENTS; FLOATING GATE TRANSISTORS;

ELECTRIC FILTERS; GATES (TRANSISTOR); MATHEMATICAL PROGRAMMING; MICROPROCESSOR CHIPS; MOSFET DEVICES; PARTICLE BEAM INJECTION;

FLASH MEMORY;

EID: 4344627312     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. D.Kahng and S. Sze, "A fbating gate and its application to memory devices," Bell Syst. Tech. J., vol. 46, p. 1288, 1967.
2. H. V. Tran, T. Blyth, D. Sowards, L. Engh, B. Nataraj, T. Dunne, H. Wang, V. Sarin, T. Lam, H. Nazarian, and G. Hu, "A 2.5 v 256-level non-volatile analog storage device using eeprom technology," 43rd IEEE International Solid-State Circuits Conference.
3. P. D. Smith, M. Kucic, and P. Hasler, "Accurate programming of analog fbating-gate arrays," in Proceedings of the IEEE International Symposium on Circuits and Systems, vol. 5, (Phoenix, AZ), pp. 489-492, May 2002.
4. P. Hasler and J. Dugger, "Correlation learning rule in fbating-gate pFET synapses," IEEE Transactions on Circuits and Systems II, 2000. in Press.