-
1
-
-
75649131497
-
Ultralow-Power operation in subthreshold regimes applying clockless logic
-
Feb
-
R. D. Jorgenson, L. Sorensen, D. Leet, M. S. Hagedorn, D. R. Lamb, T. H. Friddell, and W. P. Snapp, "Ultralow-Power operation in subthreshold regimes applying clockless logic," Proc. IEEE, vol. 98, no. 2, pp. 299-314, Feb. 2010.
-
(2010)
Proc. IEEE
, vol.98
, Issue.2
, pp. 299-314
-
-
Jorgenson, R.D.1
Sorensen, L.2
Leet, D.3
Hagedorn, M.S.4
Lamb, D.R.5
Friddell, T.H.6
Snapp, W.P.7
-
4
-
-
84857820867
-
Synchronous- Logic and globally-asynchronous-locally-synchronous (GALS) acoustic digital signal processors
-
Mar
-
K.-S. Chong, K.-L. Chang, B.-H. Gwee, and J. S. Chang, "Synchronous- Logic and globally-asynchronous-locally-synchronous (GALS) acoustic digital signal processors," IEEE J. Solid-State Circuits, vol. 47, no. 3, pp. 769-780, Mar. 2012.
-
(2012)
IEEE J. Solid-State Circuits
, vol.47
, Issue.3
, pp. 769-780
-
-
Chong, K.-S.1
Chang, K.-L.2
Gwee, B.-H.3
Chang, J.S.4
-
5
-
-
41549158226
-
A circuit for determining the optimal supply voltage to minimize energy consumption in LSI circuit operations
-
DOI 10.1109/JSSC.2008.917553
-
Y. Ikenaga,M. Nomura, Y. Nakazawa, and Y. Hagihara, "A circuit for determining the optimal supply voltage to minimize energy consumption in LSI circuit operations," IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 911-918, Apr. 2008. (Pubitemid 351464084)
-
(2008)
IEEE Journal of Solid-State Circuits
, vol.43
, Issue.4
, pp. 911-918
-
-
Ikenaga, Y.1
Nomura, M.2
Nakazawa, Y.3
Hagihara, Y.4
-
6
-
-
33947432403
-
Asynchronous techniques for system-on-chip design
-
DOI 10.1109/JPROC.2006.875789
-
A. J. Martin and M. Nystrom, "Asynchronous techniques for system-on-Chip design," Proc. IEEE, vol. 94, no. 6, pp. 1089-1120, Jun. 2006. (Pubitemid 46444961)
-
(2006)
Proceedings of the IEEE
, vol.94
, Issue.6
, pp. 1089-1120
-
-
Martin, A.J.1
Nystrom, M.2
-
7
-
-
28144457882
-
The asynchronous 24 MB on-chip level-3 cache for a dual-core itanium-family processor
-
J.Wuu, D.Weiss, C. Morganti, and M. Dreesen, "The asynchronous 24 MB on-chip level-3 cache for a dual-core itanium-family processor," in Proc. IEEE Int. Solid-State Circuits Conf., 2005, vol. 1, pp. 488-612.
-
(2005)
Proc. IEEE Int. Solid-State Circuits Conf.
, vol.1
, pp. 488-612
-
-
Wuu, J.1
Weiss, D.2
Morganti, C.3
Dreesen, M.4
-
8
-
-
0034207175
-
Analysis and design of power efficient class D amplifier output stages
-
Jun
-
J. S. Chang, M.-T. Tan, Z. Cheng, and Y.-C. Tong, "Analysis and design of power efficient class D amplifier output stages," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 47, no. 6, pp. 897-902, Jun. 2000.
-
(2000)
IEEE Trans. Circuits Syst. I, Fundam. Theory Appl.
, vol.47
, Issue.6
, pp. 897-902
-
-
Chang, J.S.1
Tan, M.-T.2
Cheng, Z.3
Tong, Y.-C.4
-
9
-
-
0027233183
-
Micropower-compatible time-multiplexed SC speech spectrum analyzer design
-
DOI 10.1109/4.179201
-
J. S. Chang and Y. C. Tong, "A micropower-compatible time-multiplexed SC speech spectrum analyzer design," IEEE J. Solid-State Circuits, vol. 28, no. 1, pp. 40-48, Jan. 1993. (Pubitemid 23612105)
-
(1993)
IEEE Journal of Solid-State Circuits
, vol.28
, Issue.1
, pp. 40-48
-
-
Chang Joseph, S.1
Tong, Y.C.2
-
10
-
-
0032123832
-
A parametric formulation of the generalized spectral subtraction method
-
Jul
-
B. L. Sim, Y. C. Tong, J. S. Chang, and C. T. Tan, "A parametric formulation of the generalized spectral subtraction method," IEEE Trans. Speech Audio Process., vol. 6, no. 4, pp. 328-337, Jul. 1998.
-
(1998)
IEEE Trans. Speech Audio Process.
, vol.6
, Issue.4
, pp. 328-337
-
-
Sim, B.L.1
Tong, Y.C.2
Chang, J.S.3
Tan, C.T.4
-
11
-
-
16444371132
-
An ultra-low-power programmable analog bionic ear processor
-
DOI 10.1109/TBME.2005.844043
-
R. Sarpeshkar, C. Salthouse, J.-J. Sit,M.W. Baker, S. M. Zhak, T. K. T. Lu, L. Turicchia, and S. Balster, "An ultra-low-power programmable analog bionic ear processor," IEEE Trans. Biomed. Eng., vol. 52, no. 4, pp. 711-727, Apr. 2005. (Pubitemid 40477181)
-
(2005)
IEEE Transactions on Biomedical Engineering
, vol.52
, Issue.4
, pp. 711-727
-
-
Sarpeshkar, R.1
Salthouse, C.2
Sit, J.-J.3
Baker, M.W.4
Zhak, S.M.5
Lu, T.K.-T.6
Turicchia, L.7
Balster, S.8
-
12
-
-
0035369246
-
Activity-driven clock design
-
DOI 10.1109/43.924824, PII S0278007001035424
-
A. H. Farrahi, C. Chen, A. Srivastava, G. Tellez, and M. Sarrafzadeh, "Activity-driven clock design," IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 20, no. 6, pp. 705-714, Jun. 2001. (Pubitemid 32576321)
-
(2001)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.20
, Issue.6
, pp. 705-714
-
-
Farrahi, A.H.1
Chen, C.2
Srivastava, A.3
Tellez, G.4
Sarrafzadeh, M.5
-
13
-
-
77949741613
-
Enabling power-efficient DVFS operations on silicon
-
Mar
-
D. Ma and R. Bondade, "Enabling power-efficient DVFS operations on silicon," IEEE Circuits Syst. Mag., vol. 10, no. 1, pp. 14-30, Mar. 2010.
-
(2010)
IEEE Circuits Syst. Mag.
, vol.10
, Issue.1
, pp. 14-30
-
-
Ma, D.1
Bondade, R.2
-
14
-
-
75649093754
-
Near-Threshold computing: Reclaiming Moore's law through energy efficient integrated circuits
-
Feb
-
R. G. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester, and T. Mudge, "Near-Threshold computing: Reclaiming Moore's law through energy efficient integrated circuits," Proc. IEEE, vol. 98, no. 2, pp. 253-266, Feb. 2010.
-
(2010)
Proc. IEEE
, vol.98
, Issue.2
, pp. 253-266
-
-
Dreslinski, R.G.1
Wieckowski, M.2
Blaauw, D.3
Sylvester, D.4
Mudge, T.5
-
16
-
-
76849102941
-
Exploring asynchronous design techniques for process-tolerant and energy-efficient subthreshold operation
-
Feb
-
C. I. Joon, P. S. Phill, and K. Roy, "Exploring asynchronous design techniques for process-tolerant and energy-efficient subthreshold operation," IEEE J. Solid-State Circuits, vol. 45, no. 2, pp. 401-410, Feb. 2010.
-
(2010)
IEEE J. Solid-State Circuits
, vol.45
, Issue.2
, pp. 401-410
-
-
Joon, C.I.1
Phill, P.S.2
Roy, K.3
-
17
-
-
84949247171
-
An asynchronous low-power 80C51 microcontroller
-
H. van Gageldonk, K. van Berkel, A. Peeters, D. Baumann, D. Gloor, and G. Stegmann, "An asynchronous low-power 80C51 microcontroller," in Proc. Int. Symp. Adv. Res. Asynch. Circuits Syst., 1998, pp. 96-107.
-
(1998)
Proc. Int. Symp. Adv. Res. Asynch. Circuits Syst.
, pp. 96-107
-
-
Van Gageldonk, H.1
Van Berkel, K.2
Peeters, A.3
Baumann, D.4
Gloor, D.5
Stegmann, G.6
-
18
-
-
33748316690
-
Desynchronization: Synthesis of asynchronous circuits from synchronous specifications
-
DOI 10.1109/TCAD.2005.860958, 1677680
-
J. Cortadella, A. Kondratyev, L. Lavagno, and C. P. Sotiriou, "Desynchronization: Synthesis of asynchronous circuits from synchronous specifications," IEEE Trans. Computer-Aided Design Integrated Circuits Syst., vol. 25, no. 10, pp. 1904-1921, Oct. 2006. (Pubitemid 44321557)
-
(2006)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.25
, Issue.10
, pp. 1904-1921
-
-
Cortadella, J.1
Kondratyev, A.2
Lavagno, L.3
Sotiriou, C.P.4
-
20
-
-
0000421548
-
The design of an asynchronous microprocessor
-
A. J. Martin, S. M. Burns, T. K. Lee, D. Borkovic, and P. J. Hazewindus, "The design of an asynchronous microprocessor," in Caltech Conf. Adv. Res. VLSI, 1989, pp. 351-373.
-
(1989)
Caltech Conf. Adv. Res. VLSI
, pp. 351-373
-
-
Martin, A.J.1
Burns, S.M.2
Lee, T.K.3
Borkovic, D.4
Hazewindus, P.J.5
-
21
-
-
34548237592
-
Energy-efficient synchronous-logic and asynchronous-logic FFT/IFFT processors
-
DOI 10.1109/JSSC.2007.903039
-
K.-S. Chong, B.-H. Gwee, and J. S. Chang, "Energy-Efficient synchronous- logic and asynchronous-logic FFT/IFFT processors," IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 2034-2045, Sep. 2007. (Pubitemid 47331298)
-
(2007)
IEEE Journal of Solid-State Circuits
, vol.42
, Issue.9
, pp. 2034-2045
-
-
Chong, K.-S.1
Gwee, B.-H.2
Chang, J.S.3
-
22
-
-
34547326807
-
A low-energy low-voltage asynchronous 8051 microcontroller core
-
1693301, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings
-
K.-L. Chang and B.-H. Gwee, "A low-energy low-voltage asynchronous 8051 microcontroller core," in Proc. IEEE Int. Symp. Circuits Syst., 2006, pp. 3181-3184. (Pubitemid 47132227)
-
(2006)
Proceedings - IEEE International Symposium on Circuits and Systems
, pp. 3181-3184
-
-
Chang, K.-L.1
Gwee, B.-H.2
-
23
-
-
84949247171
-
An asynchronous low-power 80C51 microcontroller
-
H. van Gageldonk, K. van Berkel, A. Peeters, D. Baumann, D. Gloor, and G. Stegmann, "An asynchronous low-power 80C51 microcontroller," in Proc. Int. Symp. Adv. Res. Asynch. Circuits Syst., 1998, pp. 96-107.
-
(1998)
Proc. Int. Symp. Adv. Res. Asynch. Circuits Syst.
, pp. 96-107
-
-
Van Gageldonk, H.1
Van Berkel, K.2
Peeters, A.3
Baumann, D.4
Gloor, D.5
Stegmann, G.6
-
24
-
-
70349295606
-
A necessary and sufficient timing assumption for speed-independent circuits
-
S. Keller, M. Katelman, and A. J. Martin, "A necessary and sufficient timing assumption for speed-independent circuits," in Proc. IEEE Symp. Asynch. Circuits Syst., 2009, pp. 65-76.
-
(2009)
Proc. IEEE Symp. Asynch. Circuits Syst.
, pp. 65-76
-
-
Keller, S.1
Katelman, M.2
Martin, A.J.3
-
26
-
-
0020906578
-
Worst-case static noise margin criteria for logic circuits and their mathematical equivalence
-
J. Lohstroh, E. Seevinck, and J. de Groot, "Worst-case static noise margin criteria for logic circuits and their mathematical equivalence," IEEE J. Solid-State Circuits, vol. 18, no. 6, pp. 803-807, Dec. 1983. (Pubitemid 14589971)
-
(1983)
IEEE Journal of Solid-State Circuits
, vol.SC-18
, Issue.6
, pp. 803-807
-
-
Lohstroh, J.1
Seevinck, E.2
De Groot, J.3
-
27
-
-
77954887815
-
Understanding DC behavior of subthreshold CMOS logic through closed-form analysis
-
Jul
-
M. Alioto, "Understanding DC behavior of subthreshold CMOS logic through closed-form analysis," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 7, pp. 1597-1607, Jul. 2010.
-
(2010)
IEEE Trans. Circuits Syst. I, Reg. Papers
, vol.57
, Issue.7
, pp. 1597-1607
-
-
Alioto, M.1
-
29
-
-
0029727739
-
NULL convention logic: A complete and consistent logic for asynchronous digital circuit synthesis
-
Archit. Processors
-
K.M. Fant and S. A. Brandt, "NULL convention logic: A complete and consistent logic for asynchronous digital circuit synthesis," in Proc. Int. Conf. Appl. Specific Syst., Archit. Processors, 1996, pp. 261-273.
-
(1996)
Proc. Int. Conf. Appl. Specific Syst.
, pp. 261-273
-
-
Fant, K.M.1
Brandt, S.A.2
-
30
-
-
0003557110
-
-
Ph.D. dissertation Dept. Comput. Sci., Univ. Manchester, Manchester, U.K.
-
A. Bardsley, "Implementing Balsa handshake circuits," Ph.D. dissertation, Dept. Comput. Sci., Univ. Manchester, Manchester, U.K., 2000.
-
(2000)
Implementing Balsa Handshake Circuits
-
-
Bardsley, A.1
-
31
-
-
44149109923
-
Asynchronous control network optimization using fast minimum-cycle-time analysis
-
DOI 10.1109/TCAD.2008.923238, 4526746
-
C.-F. Law, B.-H. Gwee, and J. S. Chang, "Asynchronous control network optimization using fast minimum-cycle-time analysis," IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 27, no. 6, pp. 985-998, Jun. 2008. (Pubitemid 351715236)
-
(2008)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.27
, Issue.6
, pp. 985-998
-
-
Law, C.-F.1
Gwee, B.-H.2
Chang, J.S.3
-
32
-
-
58849097136
-
Behavioral synthesis of asynchronous circuits using syntax directed translation as backend
-
Feb
-
S. F. Nielsen, J. Sparso, and J. Madsen, "Behavioral synthesis of asynchronous circuits using syntax directed translation as backend," IEEE Trans. Very Large Scale (VLSI) Syst., vol. 17, no. 2, pp. 248-261, Feb. 2009.
-
(2009)
IEEE Trans. Very Large Scale (VLSI) Syst.
, vol.17
, Issue.2
, pp. 248-261
-
-
Nielsen, S.F.1
Sparso, J.2
Madsen, J.3
-
33
-
-
77954509638
-
SNAP: A Sensor-network asynchronous processor
-
C. I. Kelly, V. Ekanayake, and R. Manohar, "SNAP: A Sensor-network asynchronous processor," in Proc. Int. Symp. Asynch. Circuits Syst., 2003, pp. 24-33.
-
(2003)
Proc. Int. Symp. Asynch. Circuits Syst.
, pp. 24-33
-
-
Kelly, C.I.1
Ekanayake, V.2
Manohar, R.3
-
34
-
-
12844285593
-
An ultra low-power processor for sensor networks
-
V. Ekanayake, I. C. Kelly, and R. Manohar, "An ultra low-power processor for sensor networks," in Int. Conf. Archit. Support Program. Languages Operat. Syst., 2004, pp. 27-36.
-
(2004)
Int. Conf. Archit. Support Program. Languages Operat. Syst.
, pp. 27-36
-
-
Ekanayake, V.1
Kelly, I.C.2
Manohar, R.3
|