Understanding DC behavior of subthreshold CMOS logic through closed-form analysis

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 57, Issue 7, 2010, Pages 1597-1607

  Alioto, Massimo ^a,b  

^a UNIVERSITY OF SIENA   (Italy)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

DC behavior; noise immunity; subthreshold CMOS logic; ultra low power; VLSI

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT DESIGN;

DC BEHAVIORS; NOISE IMMUNITY; SUBTHRESHOLD CMOS LOGIC; ULTRA LOW POWER; VLSI;

COMPUTER CIRCUITS;

EID: 77954887815     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2009.2034233     Document Type: Article

References (28)

1. J. Rabaey, J. Ammer, B. Otis, F. Burghardt, Y. H. Chee, N. Pletcher, M. Sheets, and H. Qin, "Ultra-low-power design-The Roadmap to disappearing electronics and ambient intelligence," IEEE Circuits Devices Mag., pp. 23-29, Jul./Aug. 2006.
2. A. Wang and A. Chandrakasan, "A 180-mV subthreshold FFT processor using a minimum energy design methodology," IEEE J. Solid- State Circuits, vol.40, no.1, Jan. 2005.
3. N. Verma and A. Chandrakasan, "A 256 kb 65 nm 8T subthreshold SRAM employing sense-amplifier redundancy," IEEE J. Solid-State Circuits, vol.43, no.1, pp. 141-149, Jan. 2008.
4. Y. Ramadass and A. Chandrakasan, "Minimum energy tracking loop with embedded DC-DC converter enabling ultra-low-voltage operation down to 250 mV in 65 nm CMOS," IEEE J. Solid-State Circuits, vol.43, no.1, pp. 256-265, Jan. 2008.
5. S. Hanson, B. Zhai, M. Seok, B. Cline, K. Zhou, M. Singhal, M. Minuth, J. Olson, L. Nazhandali, T. Austin, D. Sylvester, and D. Blaauw, "Exploring variability and performance in a sub-200-mV processor," IEEE J. Solid-State Circuits, vol.43, no.4, pp. 881-891, Apr. 2008.
6. A. Tajalli, M. Alioto, and Y. Leblebici, "Improving power-delay performance of ultralow-power subthreshold SCL circuits," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol.56, no.2, pp. 127-131, Feb. 2009.
7. A. Tajalli, F. K. Gurkaynak, Y. Leblebici, M. Alioto, and E. J. Brauer, "Improving the power-delay product in SCL circuits using source follower output stage," in Proc. ISCAS, Seattle, WA, May 2008, pp. 145-148.
8. A. Tajalli, M. Alioto, E. J. Brauer, and Y. Leblebici, "Design of high performance subthreshold source-coupled logic circuits," presented at the PATMOS, Lisbon, Portugal, Sep. 2008.
9. M. Alioto and Y. Leblebici, "Circuit techniques to reduce the supply voltage limit of subthreshold MCML circuits," in Proc. VLSI-SoC, Rhodes Island, Greece, Oct. 2008, pp. 239-244.
10. M. Alioto and Y. Leblebici, "Analysis and design of ultra-low power subthreshold MCML gates," in Proc. ISCAS, Taipei, Taiwan, May 2009, pp. 2557-2560.
11. A. Tajalli, E. Brauer,Y. Leblebici, and E. Vittoz, "Subthreshold sourcecoupled logic circuits for ultra-low-power applications," IEEE J. Solid- State Circuits, vol.43, no.7, pp. 1699-1710, Jul. 2008.
12. R. Keyes and T.Watson, "On power dissipation in semiconductor computing elements," Proc. IRE, vol.50, no.12, p. 2485, Dec. 1962.
13. J. Meindl and R. Swanson, "Potential improvements in power-speed performance of digital circuits," Proc. IEEE, vol.59, no.5, pp. 815-816, May 1971.
14. R. M. Swanson and J. D. Meindl, "Ion-implanted complementary MOS transistors in low-voltage circuits," IEEE J. Solid-State Circuits, vol.SC-7, no.2, pp. 146-153, Apr. 1972.
15. G. Schrom and S. Selberherr, "Ultra-low-power CMOS technologies," in Proc. Int. Semiconductor Conf. (CAS) Dig. Tech. Papers, 1996, pp. 237-246.
16. A. Bryant, J. Brown, P. Cottrell, M. Ketchen, J. Ellis-Monaghan, and J. Nowak, "Low-power CMOS at 4 kT/q," in Proc. Device Res. Conf., Jun. 2001, pp. 22-23.
17. G. Ono and M. Miyazaki, "Threshold-voltage balance for minimum supply operation," in Symp. VLSl Circuits Dig. Tech. Papers, 2002, pp. 206-209.
18. G. Ono and M. Miyazaki, "Threshold-voltage balance for minimum supply operation," IEEE J. Solid-State Circuits, vol.38, no.5, pp. 830-833, May 2003.
19. E. Vittoz, "Weak inversion for ultimate low-power logic," in Low-Power Electronics Design, C. Piguet, Ed. Boca Raton, FL: CRC Press, 2005.
20. J. Burr and A. Peterson, "Energy considerations in multichip-module based multiprocessors," in Proc. ICCD, 1991, pp. 593-600.
21. A.Wang, B. Calhoun, and A. Chandrakasan, Sub-Threshold Design for Ultra Low-Power Systems. New York: Springer, 2006.
22. B. Calhoun and A. Chandrakasan, "Static noise margin variation for sub-threshold SRAM in 65-nm CMOS," IEEE J. Solid-State Circuits, vol.41, no.7, pp. 1673-1679, Jul. 2006.
23. S. Mukhopadhyay, "Switching energy in CMOS logic: How far are we from physical limit?," 2006. [Onlineö. Available: http://nanohub.org/ resources/1250
24. S. G. Narendra and A. Chandrakasan, Leakage in Nanometer CMOS Technologies. New York: Springer, 2006.
25. Y. Tsividis, Operation and Modeling of the Transistor MOS, 2nd ed. Oxford, U.K.: Oxford University Press, 2003.
26. P. Gray and R. Meyer, Analysis and Design of Analog Integrated Circuit, 3rd ed. New York: Wiley, 1993.
27. N. Weste and D. Harris, CMOS VLSI Design. Boston, MA: Addison Wesley, 2004.
28. S. Hanson, M. Seok, D. Sylvester, and D. Blaauw, "Nanometer device scaling in subthreshold logic and SRAM," IEEE Trans. Electron Devices, vol.55, no.1, pp. 175-185, Jan. 2008.