A compact clock generator for heterogeneous GALS MPSoCs in 65-nm CMOS technology

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 21, Issue 3, 2013, Pages 566-570

  Hoppner, Sebastian ^a   Eisenreich, Holger ^a   Henker, Stephan ^a   Walter, Dennis ^a   Ellguth, Georg ^a   Schuffny, René ^a  

^a DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

All digital phase locked loop (ADPLL); digitally controlled oscillator (DCO); dynamic voltage and frequency scaling (DVFS); globally asynchronous locally synchronous (GALS); multiprocessor systems on chip (MPSoCs)

Indexed keywords

ALL DIGITAL PHASE LOCKED LOOP; DIGITALLY CONTROLLED OSCILLATORS; DYNAMIC VOLTAGE AND FREQUENCY SCALING; GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS; MULTIPROCESSOR SYSTEMS ON CHIPS;

CMOS INTEGRATED CIRCUITS; ENERGY MANAGEMENT; MULTIPROCESSING SYSTEMS; VLSI CIRCUITS;

ELECTRIC CLOCKS;

EID: 84874657234     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2012.2187224     Document Type: Article

References (31)

1. U. Ramacher, "Software-defined radio prospects for multistandard mobile phones," Computer, vol. 40, no. 10, pp. 62-69, Oct. 2007.
2. D. Schinkel, E. Mensink, E. Klumperink, E. Ven Tuijl, and B. Nauta, "Low-power, high-speed transceivers for network-on-chip communication," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 17, no. 1, pp. 12-21, Jan. 2009.
3. S. Scholze,H. Eisenreich, S. Höppner, G. Ellguth, S. Henker, M. Ander, S. Hänzsche, J. Partzsch, C.Mayr, and R. Schüffny, "A 32 GBit/s communication SoC for a waferscale neuromorphic system," Integr., VLSI J., vol. 45, no. 1, pp. 61-75, 2012.
4. T. Limberg,M.Winter, M. Bimberg, R. Klemm, E.Matus,M. Tavares, G. Fettweis, H. Ahlendorf, and P. Robelly, "A fully programmable 40 GOPS SDR single chip baseband for LTE/WiMAX terminals," in Proc. Solid-State Circuits Conf., 2008, pp. 466-469.
5. S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, "An 80-tile sub-100-W teraflops processor in 65-nm CMOS," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 29-41, Jan. 2008.
6. Z. Yu and B. Baas, "High performance, energy efficiency, and scalability with GALS chip multiprocessors," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 17, no. 1, pp. 66-79, Jan. 2009.
7. W. Kim, M. Gupta, G.-Y.Wei, and D. Brooks, "System level analysis of fast, per-core DVFS using on-chip switching regulators," in Proc. IEEE 14th Int. Symp. High Perform. Comput. Arch. (HPCA), 2008, pp. 123-134.
8. D. Truong, W. Cheng, T. Mohsenin, Z. Yu, A. Jacobson, G. Landge, M. Meeuwsen, C. Watnik, A. Tran, Z. Xiao, E. Work, J. Webb, P. Mejia, and B. Baas, "A 167-processor computational platformin 65 nm CMOS," IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1130-1144, Apr. 2009.
9. R. Jipa, "Dedicated solution for local clock programing in GALS designs," in Proc. Int. Semicond. Conf. (CAS), 2008, pp. 393-396.
10. A. Sobczyk, A. Luczyk, and W. Pleskacz, "Controllable local clock signal generator for deep submicronGALS architectures," in Proc. 11th IEEE Workshop Design Diagnos. Electron. Circuits Syst., 2008, pp. 1-4.
11. S. Moore, G. Taylor, P. Cunningham, R. Mullins, and P. Robinson, "Self calibrating clocks for globally asynchronous locally synchronous systems," in Proc. Int. Conf. Comput. Design, 2000, pp. 73-78.
12. L. Xiu, "A flying-adder on-chip frequency generator for complex SoC environment," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 12, pp. 1067-1071, Dec. 2007.
13. J. A. Tierno, A. V. Rylyakov, and D. J. Friedman, "A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65 nm SOI," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 42-51, Jan. 2008.
14. N. Da Dalt, "A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 1, pp. 21-31, Jan. 2005. (Pubitemid 40173701)
15. H. Eisenreich, C. Mayr, S. Henker, M. Wickert, and R. Schüffny, "A novel ADPLL design using successive approximation frequency control," Microelectron. J., vol. 40, pp. 1613-1622, Nov. 2009.
16. J. A. McNeill and D. Ricketts, The Designer's Guide to Jitter in Ring Oscillators. New York: Springer, 2009.
17. B. Floyd, "Sub-integer frequency synthesis using phase-rotating frequency dividers," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 7, pp. 1823-1833, Jul. 2008.
18. K. Shu and E. Sinchez-Sinencio, CMOS PLL Synthesizers: Analysis and Design. New York: Springer, 2005.
19. S. Höppner, S. Henker, H. Eisenreich, and R. Schüffny, "An open-loop clock generator for fast frequency scaling in 65 nm CMOS technology," in Proc. Mixed Design Integr. Circuits Syst., 2011, pp. 264-269.
20. R. Ven de Beek, E. Klumperink, C. Vaucher, and B. Nauta, "Low-jitter clock multiplication: a comparison between PLLs and DLLs," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 49, no. 8, pp. 555-566, Aug. 2002.
21. JEDEC Solid State Technology Association, Arlington, VA, "JESD79-2F DDR2 SDRAM Specification," 2009.
22. JEDEC Solid State Technology Association, Arlington, VA, "JESD79-3E DDR3 SDRAM Specification," 2010.
23. W. Yin, R. Inti, A. Elshazly, B. Young, and P. K. Hanumolu, "A 0.7-to-3.5 GHz 0.6-to-2.8 mW highly digital phase-locked loop with bandwidth tracking," IEEE J. Solid-State Circuits, DOI: 10.1109/JSSC.2011.2157259.
24. P.-H. Hsieh, J. Maxey, and C.-K. Yang, "A phase-selecting digital phase-locked loop with bandwidth tracking in 65-nm CMOS technology," IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 781-792, Apr. 2010.
25. C.-C. Hung and S.-I. Liu, "A leakage-compensated PLL in 65-nm CMOS technology," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 7, pp. 525-529, Jul. 2009.
26. J.-Y. Chang and S.-I. Liu, "A phase-locked loop with background leakage current compensation," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 9, pp. 666-670, Sep. 2010.
27. J.-Y. Chang and S.-I. Liu, "A 1.5 GHz phase-locked loop with leakage current suppression in 65 nm CMOS," IET Circuits, Devices Syst., vol. 3, no. 6, pp. 350-358, Dec. 2009.
28. M.-W. Chen, D. Su, and S. Mehta, "A calibration-free 800 MHz fractional-N digital PLL with embedded TDC," IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2819-2827, Dec. 2010.
29. W. Grollitsch, R. Nonis, and N. Da Dalt, "A 1.4 PSRMS-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65 nm CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers (ISSCC), 2010, pp. 478-479.
30. A. Rylyakov, J. Tierno, G. English, M. Sperling, and D. Friedman, "A wide tuning range (1 GHz-to-15 Ghz) fractional-N all-digital PLL in 45 nm SOI," in Proc. Custom Integr. Circuits Conf., 2008, pp. 431-434.
31. X. Gao, E. Klumperink, P. Geraedts, and B. Nauta, "Jitter analysis and a benchmarking figure-of-merit for phase-locked loops," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 2, pp. 117-121, Feb. 2009.