A calibration-free 800 MHz fractional-N digital PLL with embedded TDC

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 12, 2010, Pages 2819-2827

  Chen, Mike Shuo Wei ^a   Su, David ^a   Mehta, Srenik ^a  

^a Atheros Communications   (United States)

Author keywords

ADPLL; calibration free; clock generation; digital PLL; embedded TDC; interpolation flip flop; mismatch filtering; phase locked loop; time to digital converter

Indexed keywords

ADPLL; CALIBRATION FREE; CLOCK GENERATION; DIGITAL PLL; EMBEDDED TDC; MISMATCH FILTERING; TIME TO DIGITAL CONVERTERS;

CALIBRATION; COLOR TELEVISION; FLIP FLOP CIRCUITS; INTERPOLATION; OSCILLATORS (ELECTRONIC);

FREQUENCY CONVERTERS;

EID: 78650051029     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2074950     Document Type: Conference Paper

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