A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2008, Pages 431-434

  Rylyakov, Alexander ^a   Tierno, Jose ^a   English, George ^b   Sperling, Michael ^b   Friedman, Daniel ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MULTIPLICATION FACTORS; PERIOD JITTER; REFERENCE CLOCKS; WIDE TUNING RANGES;

JITTER; PHASE LOCKED LOOPS; TUNING;

INTEGRATED CIRCUITS;

EID: 57949105098     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2008.4672113     Document Type: Conference Paper

References (7)

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3. .I.A. Tierno, A.V. Rylyakov, D. Friedman, "A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI", IEEE J. Solid State Circuits, vol. 43, no. 1, pp. 42-51, Jan. 2008.
4. A. Rylyakov, J. Tierno, D. Turker, et. al., "A Modular All Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS", ISSCC Dig. Tech. Papers, pp. 516-517, Feb. 2008.
5. S. Lee, B. Jagannathan, S. Narasimha, et.al., "Record RF performance of 45-nm SOI CMOS Technology", 2007 IEEE International Electron Devices Meeting (IEDM), pp. 255-258, Dec. 2007.
6. N. DaDalt, "A Design-Oriented Study of the Nonlinear Dynamics of Digital Bang-Bang PLLs," IEEE Trans. on Circ. Syst. Parti, vol. 52, pp. 21-31, January 2005.
7. V. Kratyuk, P. Hanumolu, K. Ok, K. Mayaram, and U. Moon, "A digital PLL with a stochastic time-to-digital converter, " IEEE Symp. VLSI Circuits, pp. 38-39, Jun. 2006.