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Volumn 17, Issue 1, 2009, Pages 66-79

High performance, energy efficiency, and scalability with GALS chip multiprocessors

Author keywords

Array processor; Chip multiprocessor; Energy efficient; Globally asynchronous locally synchronous (GALS); Low power; Scalable

Indexed keywords

CLOCKS; ENERGY EFFICIENCY; MULTIPROCESSING SYSTEMS; SYSTEMS ANALYSIS; VOLTAGE CONTROL;

EID: 58849129010     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2001947     Document Type: Article
Times cited : (29)

References (32)
  • 3
    • 0003657403 scopus 로고
    • Globally-asynchronous locally-synchronous systems,
    • Ph.D. dissertation, Dept. Comput. Sci, Stanford Univ, Stanford, CA, Oct
    • D. M. Chapiro, "Globally-asynchronous locally-synchronous systems," Ph.D. dissertation, Dept. Comput. Sci., Stanford Univ., Stanford, CA, Oct. 1984.
    • (1984)
    • Chapiro, D.M.1
  • 6
    • 18744363054 scopus 로고    scopus 로고
    • Toward a multiple clock/voltage island design style for power-aware processors
    • May
    • E. Talpes and D. Marculescu, "Toward a multiple clock/voltage island design style for power-aware processors," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 5, pp. 591-603, May 2005.
    • (2005) IEEE Trans. Very Large Scale Integr. (VLSI) Syst , vol.13 , Issue.5 , pp. 591-603
    • Talpes, E.1    Marculescu, D.2
  • 7
    • 1542269334 scopus 로고    scopus 로고
    • A critical analysis of application-adaptive multiple clock processor
    • Aug
    • E. Talpes and D. Marculescu, "A critical analysis of application-adaptive multiple clock processor," in Proc. Int. Symp. Low Power Electron. Des., Aug. 2003, pp. 278-281.
    • (2003) Proc. Int. Symp. Low Power Electron. Des , pp. 278-281
    • Talpes, E.1    Marculescu, D.2
  • 9
    • 2942639661 scopus 로고    scopus 로고
    • Optimal partitioning of globally asynchronous locally synchronous processor arrays
    • Apr
    • A. Upadhyay, S. R. Hasan, and M. Nekili, "Optimal partitioning of globally asynchronous locally synchronous processor arrays," in Proc. Great Lakes Symp. VLSI (GLSVLSI), Apr. 2004, pp. 26-28.
    • (2004) Proc. Great Lakes Symp. VLSI (GLSVLSI) , pp. 26-28
    • Upadhyay, A.1    Hasan, S.R.2    Nekili, M.3
  • 10
    • 34648839900 scopus 로고    scopus 로고
    • A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains
    • Oct
    • R. W. Apperson, Z. Yu, M. Meeuwsen, T. Mohsenin, and B. Baas, "A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains," IEEE Trans. Very Large Scale Integr: (VLSI) Syst., vol. 15, no. 10, pp. 1125-1134, Oct. 2007.
    • (2007) IEEE Trans. Very Large Scale Integr: (VLSI) Syst , vol.15 , Issue.10 , pp. 1125-1134
    • Apperson, R.W.1    Yu, Z.2    Meeuwsen, M.3    Mohsenin, T.4    Baas, B.5
  • 14
    • 0034314477 scopus 로고    scopus 로고
    • A 1-V heterogeneous reconfigurable DSPIC for wireless baseband digital signal processing
    • Nov
    • H. Zhang, V. Prabhu, V. George, M. Wan, M. Benes, A. Abnous, and J. M. Rabaey, "A 1-V heterogeneous reconfigurable DSPIC for wireless baseband digital signal processing," IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1697-1704, Nov. 2000.
    • (2000) IEEE J. Solid-State Circuits , vol.35 , Issue.11 , pp. 1697-1704
    • Zhang, H.1    Prabhu, V.2    George, V.3    Wan, M.4    Benes, M.5    Abnous, A.6    Rabaey, J.M.7
  • 15
    • 34548814965 scopus 로고    scopus 로고
    • A telecom baseband circuit based on an asynchronous network-on-chip
    • Feb
    • D. Lattard et al., "A telecom baseband circuit based on an asynchronous network-on-chip," in Proc. ISSCC, Feb. 2007, pp. 258-259.
    • (2007) Proc. ISSCC , pp. 258-259
    • Lattard, D.1
  • 16
    • 84863763384 scopus 로고    scopus 로고
    • TeraOPS hardware: A new massively-parallel MIMD computing fabric IC
    • Aug, Session 5
    • A. M. Jones and M. Butts, "TeraOPS hardware: A new massively-parallel MIMD computing fabric IC," in Proc. Hotchips, Aug. 2006, Session 5.
    • (2006) Proc. Hotchips
    • Jones, A.M.1    Butts, M.2
  • 18
    • 34548858682 scopus 로고    scopus 로고
    • An 80-tile 1.28 TFLOPS network-on-chip in 65 nm CMOS
    • Feb
    • S. Vangal et al., "An 80-tile 1.28 TFLOPS network-on-chip in 65 nm CMOS," in Proc. ISSCC, Feb. 2007, pp. 98-99.
    • (2007) Proc. ISSCC , pp. 98-99
    • Vangal, S.1
  • 19
    • 17044404691 scopus 로고    scopus 로고
    • A full-rate software implementation of an IEEE 802.1 la compliant digital baseband transmitter
    • Oct
    • M. Meeuwsen, O. Sattari, and B. Baas, "A full-rate software implementation of an IEEE 802.1 la compliant digital baseband transmitter," in Proc. IEEE Workshop Signal Process. Syst., Oct. 2004, pp. 297-301.
    • (2004) Proc. IEEE Workshop Signal Process. Syst , pp. 297-301
    • Meeuwsen, M.1    Sattari, O.2    Baas, B.3
  • 22
    • 0036294823 scopus 로고    scopus 로고
    • Power and performance evaluation of globally asynchronous locally synchronous processors
    • May
    • A. Iyer and D. Marculescu, "Power and performance evaluation of globally asynchronous locally synchronous processors," in Proc. Int. Symp. Comput. Arch., May 2002, pp. 158-168.
    • (2002) Proc. Int. Symp. Comput. Arch , pp. 158-168
    • Iyer, A.1    Marculescu, D.2
  • 24
    • 33749353560 scopus 로고    scopus 로고
    • Performance and power analysis of globally asynchronous locally synchronous multi-processor systems
    • Mar
    • Z. Yu and B. Baas, "Performance and power analysis of globally asynchronous locally synchronous multi-processor systems," in Proc. IEEE Comput. Soc. Ann. Symp. VLSI, Mar. 2006, pp. 378-384.
    • (2006) Proc. IEEE Comput. Soc. Ann. Symp. VLSI , pp. 378-384
    • Yu, Z.1    Baas, B.2
  • 25
    • 58849140604 scopus 로고    scopus 로고
    • Fast Fourier transform on a distributed digital signal processor,
    • M.S. thesis, Elect. Comput. Eng. Dept, UC Davis, Davis, CA
    • O. Sattari, "Fast Fourier transform on a distributed digital signal processor," M.S. thesis, Elect. Comput. Eng. Dept., UC Davis, Davis, CA, 2004.
    • (2004)
    • Sattari, O.1
  • 26
    • 0141649524 scopus 로고    scopus 로고
    • C. E. Dike, N. A. Kurd, P. Patra, and J. Barkatullah, A design for digital, dynamic clock deskew, in Proc. Symp. VLSI Circuits, Jun. 2003, pp. 2.1-24.
    • C. E. Dike, N. A. Kurd, P. Patra, and J. Barkatullah, "A design for digital, dynamic clock deskew," in Proc. Symp. VLSI Circuits, Jun. 2003, pp. 2.1-24.
  • 30
    • 34547241854 scopus 로고    scopus 로고
    • Clock trees: Differential or single ended?
    • Mar
    • D. C. Sekar, "Clock trees: Differential or single ended?," in Proc. Int. Symp. Quality Electron. Des., Mar. 2005, pp. 545-553.
    • (2005) Proc. Int. Symp. Quality Electron. Des , pp. 545-553
    • Sekar, D.C.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.