Low-resolution DAC-driven linearity testing of higher resolution ADCs using polynomial fitting measurements

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 21, Issue 3, 2013, Pages 454-464

  Kook, Sehun ^a   Choi, Hyun Woo ^a   Chatterjee, Abhijit ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Analog to digital converters (ADCs); automated test equipment (ATE); built in self test (BIST); device under test (DUT); differential nonlinearity; digital to analog converters (DACs); integral nonlinearity

Indexed keywords

ANALOG TO DIGITAL CONVERTERS; AUTOMATED TEST EQUIPMENT; DEVICE UNDER TEST; DIFFERENTIAL NONLINEARITY; DIGITAL-TO-ANALOG CONVERTERS; INTEGRAL NONLINEARITY;

ANALOG TO DIGITAL CONVERSION; BUILT-IN SELF TEST; COSTS; DIGITAL INTEGRATED CIRCUITS; DIGITAL STORAGE; GRAPHIC METHODS; SIGNAL GENERATORS; TRANSFER FUNCTIONS;

SOFTWARE TESTING;

EID: 84874652550     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2012.2190433     Document Type: Article

References (21)

1. M. Mahoney, DSP-Based Testing of Analog and Mixed Signal Circuits. New York: Wiley, 1987.
2. M. Burns and G. W. Roberts, An Introduction to Mixed-Signal IC Test and Measurement. New York: Oxford Univ. Press, 2000.
3. J. Doernberg, H.-S. Lee, and D. A. Hodges, "Full-speed testing of A/D converters," IEEE J. Solid-State Circuits, vol. 19, no. 6, pp. 820-827, Dec. 1984.
4. J. Blair, "Histogram measurement of ADC nonlinearities using sine waves," IEEE Trans. Instrum. Meas., vol. 43, no. 3, pp. 373-383, Jun. 1994.
5. S. K. Sunter and N. Nagi, "A simplified polynomial-fitting algorithm for DAC and ADC BIST," in Proc. Int. Test Conf., Mar. 1997, pp. 389-395.
6. J.-L. Huang, C.-K. Ong, and K.-T. Cheng, "A BIST scheme for on-chip ADC and DAC testing," in Proc. Design Automat. Test Europe Conf. Exhibit., Mar. 2000, pp. 216-220.
7. J. Ren, J. Feng, and H. Ye, "A novel linear histogram BIST for ADC," in Proc. Int. Conf. Solid-State Integr.-Circuit Technol., Oct. 2008, pp. 2099-2102.
8. P. D. Capofreddi and B. A. Wooley, "The use of linear models in A/D converter testing," IEEE Trans. Circuits Syst. I Reg. Papers, vol. 44, no. 12, pp. 1105-1113, Dec. 1997. (Pubitemid 127768211)
9. S. Cherubal and A. Chatterjee, "Optimal linearity testing of analog-to-digital converters using a linear model," IEEE Trans. Circuits Syst. I Reg. Papers, vol. 50, no. 3, pp. 317-327, Mar. 2003.
10. C. Wegener and M. P. Kennedy, "Linear model-based testing of ADC nonlinearities," IEEE Trans. Circuits Syst., vol. 51, no. 1, pp. 213-217, Jan. 2004.
11. F. Adamo, F. Attivissimo, N. Giaquinto, and M. Savino, "FFT test of A/D converters to determine the integral nonlinearity," IEEE Trans. Instrum. Meas., vol. 51, no. 5, pp. 1050-1054, Oct. 2002.
12. G. Yu, P. Li, and W. Dong, "Achieving low-cost linearity test and dignosis of sigma delta ADCs via frequency-domain nonlinear analysis and macromodeling," in Proc. Int. Symp. Quality Electron. Design, San Jose, CA, Mar. 2007, pp. 513-518. (Pubitemid 47298245)
13. B. Olleta, D. Chen, and R. L. Geiger, "A dynamic element matching approach to ADC testing," in Proc. IEEE Midw. Symp. Circuits Syst., Aug. 2002, pp. 549-552.
14. B. Olleta, L. Juffer, D. Chen, and R. L. Geiger, "A deterministic dynamic element matching approach to ADC testing," in Proc. IEEE Int. Symp. Circuits Syst., May 2003, pp. 533-536.
15. B. Olleta, H. Jiang, D. Chen, and R. L. Geiger, "A deterministic dynamic element matching approach for testing high-resolution ADCs with low-accuracy excitations," IEEE Trans. Instrum. Meas., vol. 55, no. 3, pp. 902-915, Jun. 2006. (Pubitemid 43820866)
16. H. Jiang, B. Olleta, D. Chen, and R. L. Geiger, "Testing high-resolution ADCs with low-resolution/accuracy deterministic dynamic element matched DACs," IEEE Trans. Instrum. Meas., vol. 56, no. 5, pp. 1753-1762, Jun. 2007. (Pubitemid 47484647)
17. L. Jin, K. Parthasarathy, D. Chen, and R. L. Geiger, "Accurate testing of analog-to-digital converters using low linearity signals with stimulus errors identification and removal," IEEE Trans. Instrum. Meas., vol. 54, no. 3, pp. 1188-1199, Jun. 2005. (Pubitemid 40843545)
18. L. Jin, D. Chen, and R. L. Geiger, "SEIR linearity testing of precision A/D converters in nonstationary environments with center-symmetric interleaving," IEEE Trans. Instrum. Meas., vol. 56, no. 5, pp. 1776-1785, Jun. 2007. (Pubitemid 47455900)
19. E. J. Peralias, M. A. Jalon, and A. Rueda, "Simple evaluation of the nonlinearity signature of an ADC using a spectral approach," VLSI Design, vol. 2008, no. 4, pp. 1-8, Jul. 2008.
20. D. M. Hawkins, "The problem of overfitting," J. Chem. Inform. Comput. Sci., vol. 44, no. 1, pp. 1-12, 2004.
21. S. Lawrence and L. Giles, "Overfitting and neural networks: Conjugate gradient and backpropagation," in Proc. Int. Joint Conf. Neural Netw., Jul. 2000, pp. 114-119.