A novel linear histogram BIST for ADC

International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT

Volumn , Issue , 2008, Pages 2099-2102

  Ren, Jianguo ^a   Feng, Jianhua ^a   Ye, Hongfei ^a  

^a PEKING UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

HARDWARE OVERHEADS; INPUT SIGNALS; SPACE DECOMPOSITIONS; STATIC PARAMETERS; STATIC TESTING; TEST RESULTS; TESTING TIME;

INTEGRATED CIRCUITS;

MULTICARRIER MODULATION;

EID: 60649084241     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICSICT.2008.4734981     Document Type: Conference Paper

References (6)

1. th Asian Test Symposium (ATS'03), pp 124-127.
2. N.Nagi, A. Chatterjee, J. Abraham, "A Signature Analyzer for Analog and Mixed-Signal Circuits", Proc. ICCAD, 1994,pp.84-87
3. F.Azais, S.Bernard, Y. Bertrand and M.Renovell, " Implementation of a linear histogram BIST for ADCs", in Proc DATE 2001, Mar. 2001, pp 590-595.
4. M.Renovell, F.Azais, S.Bernard and Y.Bertrand, "Hardware resource minimization for histogram-based ADC BIST", VLSI Test Symposium, 2000 Proceedings 18th IEEE, 30 April-4 May 2000 Page(s):247-252
5. Mark Burns and Gordon W. Roberts, "An Introduction to Mixed-Signal IC Test and Measurement", Oxford University Press, ISBN 0-19-514016-8, 2001
6. Benoit Provost and Edgar Sanchez-sinencio, "On-Chip Ramp Generation for Mixed-Signal BIST and ADC Self-Test", IEEE Journal of Solid-state Circuits, Vol.38, No.2, pp263-273, 2003.