Testing high-resolution ADCs with low-resolution/accuracy deterministic dynamic element matched DACs

IEEE Transactions on Instrumentation and Measurement

Volumn 56, Issue 5, 2007, Pages 1753-1762

  Jiang, Hanjun ^a   Olleta, Beatriz ^b   Chen, Degang ^c   Geiger, Randall L ^c  

^a TSINGHUA UNIVERSITY   (China)

^b Allegro Microsystems Argentina   (Argentina)

^c Iowa State University   (United States)

Author keywords

Analog to digital converter (ADC) testing; Differential nonlinearity (DNL); Digital to analog converter (DAC); Dynamic element matching (DEM); Integral nonlinearity (INL)

Indexed keywords

COMPUTER SIMULATION; DIGITAL TO ANALOG CONVERSION; ELECTRIC POTENTIAL; RAMP GENERATORS;

DETERMINISTIC DYNAMIC ELEMENT MATCHING; DIFFERENTIAL NONLINEARITY; INTEGRAL NONLINEARITY;

ANALOG TO DIGITAL CONVERSION;

EID: 34748833471     PISSN: 00189456     EISSN: None     Source Type: Journal    
DOI: 10.1109/TIM.2007.903621     Document Type: Article

References (31)

1. Semiconductor Industry Association, 2001 Edition International Technology Roadmap for Semiconductors, 2001. [Online]. Available: http://public.itrs.net/Files/2001ITRS/Home.htm
2. M. Burns and G. W. Roberts, An Introduction to Mixed-Signal IC Test and Measurement. New York: Oxford Univ. Press, 2000.
3. K. L. Parthasarathy, L. Jin, D. Chen, and R. L. Geiger, "A modified histogram approach for accurate self-characterization of analog-to-digital converters," in Proc. IEEE Int. Symp. Circuits Syst., Scottsdale, AZ, May 2002, vol. 2, pp. II-376-II-379.
4. J. Wang, E. Sanchez-Sinencio, and F. Maloberti, "Very linear ramp-generators for high resolution ADC BIST and calibration," in Proc. 43rd IEEE Midwest Symp. Circuits Syst., East Lansing, MI, Aug. 2000, pp. 908-911.
5. S. Bernard, F. Azais, Y. Bertrand, and M. Renovell, "A high accuracy triangle-wave signal generator for on-chip ADC testing," in Proc. IEEE Eur. Test Workshop, Corfu, Greece, May 2002, pp. 89-94.
6. B. Provost and E. Sanchez-Sinencio, "On-chip ramp generators for mixed-signal BIST and ADC self-test," IEEE J. Solid-State Circuits vol. 38, no. 2, pp. 263-273, Feb. 2003.
7. B. Dufort and G. W. Roberts, "Signal generation using periodic single and multi-bit sigma-delta modulated streams," in Proc. Int. Test Conf., Nov. 1997, pp. 396-405.
8. M. F. Toner and G. W. Roberts, "A frequency response, harmonic distortion, and intermodulation distortion test for BIST of a sigma-delta ADC," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 43, no. 8, pp. 608-613, Aug. 1996.
9. K. Arabi and B. Kaminska, "Oscillation built-in self test (OBIST) scheme for functional and structural testing of analog and mixed-signal integrated circuits," in Proc. Int. Test Conf., Nov. 1997, pp. 786-795.
10. F. Azaiz, S. Bernard, Y. Bertrand, and M. Renovell, "Towards an ADC BIST scheme using the histogram test technique," in Proc. IEEE Eur. Test Workshop, May 2000, pp. 53-58.
11. R. de Vries, T. Zwemstra, E. M. J. G. Bruls, and P. P. L. Regtien, "Built-in self-test methodology for A/D converters," in Proc. Eur. Des. Test Conf., Mar. 1997, pp. 353-358.
12. L. Jin, K. L. Parthasarathy, D. Chen, and R. L. Geiger, "A blind identification approach to digital calibration of analog-to-digital converters for built-in-self-test," in Proc. IEEE Int. Symp. Circuits Syst., Scottsdale, AZ, May 2002, vol. 2, pp. 788-791.
13. L. Jin, K. Parthasarathy, T. Kuyel, D. Chen, and R. L. Geiger, "Linearity testing of precision analog-to-digital converters using stationary nonlinear inputs," in Proc. Int. Test Conf., Sep. 2003, pp. 218-227.
14. K. Parthasarathy, T. Kuyel, D. Price, L. Jin, D. Chen, and R. L. Geiger, "BIST and production testing of ADCs using imprecise stimulus," ACM Trans. Design Autom. Electron. Syst., vol. 8, no. 4, pp. 522-545, Oct. 2003.
15. R. J. Van De Plassche, "Dynamic element matching for high-accuracy monolithic D/A converters," IEEE J. Solid-State Circuits, vol. SSC-11, no. 6, pp. 795-800, Dec. 1976.
16. L. R. Carley, "A noise-shaping coder topology for 15+ bit converters," IEEE J. Solid-State Circuits, vol. 24, no. 2, pp. 267-273, Apr. 1989.
17. H. T. Jensen and I. Galton, "A low-complexity dynamic element matching DAC for direct digital synthesis," IEEE Trans. Circuits Syst., vol. 45, no. 1, pp. 13-27, Jan. 1998.
18. H. T. Jensen and I. Galton, "An analysis of the partial randomization dynamic element matching technique," IEEE Trans. Circuits Syst. II vol. 45, no. 12, pp. 1538-1549, Dec. 1998.
19. B. H. Leung and S. Sutarja, "Multibit ∑-Δ A/D converter incorporating a novel class of dynamic element matching techniques," IEEE Trans. Circuits Syst. II, vol. 39, no. 1, pp. 35-51, Jan. 1992.
20. R. T. Baird and T. S. Fiez, "Linearity enhancement of multibit Δ∑ A/D and D/A converters using data weighted averaging," IEEE Trans. Circuits Syst. II, vol. 42, no. 12, pp. 753-762, Dec. 1995.
21. D. Cini, C. Samori, and A. L. Lacaita, "Double-index averaging: A novel technique for dynamic element matching in ∑-Δ A/D converters," IEEE Trans. Circuits Syst. II, vol. 46, no. 4, pp. 353-358, Apr. 1999.
22. R. E. Radke, A. Eshraghi, and T. S. Fiez, "A 14-bit current-mode ∑Δ DAC based upon rotated data weighted averaging," IEEE J. Solid-State Circuits, vol. 35, no. 8, pp. 1074-1084, Aug. 2000.
23. I. Fujimori, L. Longo, A. Hairapetian, K. Seiyama, S. Kosic, J. Cao, and S.-L. Chan, "A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8x oversampling ratio," IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1820-1828, Dec. 2000.
24. R. Adams et al., "Data-directed scrambler for multi-bit noise shaping D/A converters," U.S. Patent 5 404 142, Apr. 4, 1995.
25. B. Olleta, D. Chen, and R. L. Geiger, "A dynamic element matching approach to ADC testing," in Proc. 45th IEEE Midwest Symp. Circuits Syst., Tulsa, OK, Aug. 2002, vol. 2, pp. II-549-II-552.
26. B. Olleta, L. Juffer, D. Chen, and R. L. Geiger, "A deterministic dynamic element approach to ADC testing," in Proc. IEEE Int. Symp. Circuits Syst., Bangkok, Thailand, May 2003, vol. 5, pp. V-533-V-535.
27. H. Jiang, B. Olleta, D. Chen, and R. Geiger, "Parameter optimization of deterministic dynamic element matching DACs for accurate and cost-effective ADC testing," in Proc. IEEE Int. Symp. Circuits Syst. Vancouver, BC, Canada, May 2004, vol. 1, pp. I-924-I-927.
28. B. Olleta, H. Jiang, D. Chen, and R. L. Geiger, "Testing high resolution ADCs using deterministic dynamic element matching," in Proc. IEEE Int. Symp. Circuits Syst., Vancouver, BC, Canada, May 2004, vol. 1, pp. I-920-I-923.
29. B. Olleta, H. Jiang, D. Chen, and R. L. Geiger, "A deterministic dynamic element matching approach for testing high-resolution ADCs with low-accuracy excitations," IEEE Trans. Instrum. Meas., vol. 55, no. 3, pp. 902-915, Jun. 2006.
30. D. A. Johns and K. Martin, Analog Integrated Circuit Design. Hoboken, NJ: Wiley, 1997.
31. J. M. Rabaey, Digital Integrated Circuits: A Design Perspective. Englewood Cliffs, NJ: Prentice-Hall, 1996.