Subthreshold performance of gate engineered FinFET devices and circuit with high-k dielectrics

Microelectronics Reliability

Volumn 53, Issue 3, 2013, Pages 499-504

  Nirmal, D ^a   Vijayakumar, P ^b   Thomas, Divya Mary ^a   Jebalin, Binola K ^a   Mohankumar, N ^c  

^a KARUNYA UNIVERSITY   (India)

^b KARPAGAM COLLEGE OF ENGINEERING   (India)

^c SKP Engineering College   (India)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT APPLICATION; DRAIN-INDUCED BARRIER LOWERING; DUAL MATERIAL GATE; DUAL MATERIALS; ENGINEERING TECHNIQUES; EQUIVALENT OXIDE THICKNESS; FIN WIDTHS; FINFET DEVICES; FINFETS; GATE OXIDE; GATE WORK FUNCTION; HIGH-K DIELECTRIC; HIGH-K DIELECTRIC MATERIALS; INTRINSIC GATE CAPACITANCE; K-VALUES; NANO SCALE; OFF CURRENT; ON CURRENTS; OUTPUT RESISTANCE; PAPER ANALYSIS; SHORT-CHANNEL EFFECT; SUBTHRESHOLD; SYSTEM-ON-CHIP APPLICATIONS; TRANSCONDUCTANCE GENERATION FACTORS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ELECTRIC RESISTANCE; FINS (HEAT EXCHANGE); GATE DIELECTRICS; GATES (TRANSISTOR); INTEGRATED CIRCUITS; MOS DEVICES; MOSFET DEVICES; TRANSCONDUCTANCE;

DIELECTRIC MATERIALS;

EID: 84874650568     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2012.09.008     Document Type: Article

References (19)

1. D. Nirmal, B. Nalini, and P. Vijayakumar Nanosized high k dielectric material for FinFET Integr Ferroelectrics 121 1 2010 31 35
2. D.J. Frank, R.H. Dennard, E. Nowak, P.M. Solomon, Y. Taur, and H.S.P. Wong Device scaling limits of Si MOSFETs and their application dependencies Proc IEEE 89 3 2001 259 288
3. J.P. Colinge Multiple-gate SOI MOSFETs Solid State Electron 48 6 2004 897 905
4. Nirmal D, Thomas Divya Mary, Shruti K, Samuel Patrick Chella, Vijaya Kumar P, Mohan Kumar N. Impact of gate engineering on double gate MOSFETs using high-k dielectrics. In: Proceedings of the 3rd international conference on electronics computer technology, vol. 1, 2011. p. 31-4.
5. N. Mohan Kumar, Syamal Binit, and C.K. Sarkar Investigation of novel attributes of single halo dual-material double gate MOSFETs for analog/RF applications Microelectron Reliab 49 12 2009 1491 1497
6. S. Chakraborty, A. Mallik, C.K. Sarkar, and V. Ramgopal Rao Impact of halo doping on the subthreshold performance of deep-sub micrometer CMOS devices and circuits for ultralow power analog/mixed signal applications IEEE Trans Electron Dev 54 2 2007 241 248 (Pubitemid 46358409)
7. N. Mohan Kumar, Syamal Binit, and C.K. Sarkar Performance and optimization of dual material gate (DMG) short channel BULK MOSFETs for analog/mixed signal applications Int J Electron 96 6 2009 603 611
8. J. Yuan, and J.C.S. Woo A novel split-gate MOSFET design realized by a fully silicided gate process for the improvement of transconductance and output resistance IEEE Electron Dev Lett 26 11 2005 829 831 (Pubitemid 41622535)
9. D. Nirmal, and P. Vijaya Kumar Fin field effect transistors performance in analog and RF for high-k dielectrics Defence Sci J 61 3 2011 35 240
10. D. Nirmal, K. Shruti, Divya Mary Thomas, Patrick Chella Samuel, P. Vijaya Kumar, and N. Mohan Kumar Impact of channel engineering on FinFETs using high-k dielectrics Int J Micro Nano Electron, Circ Syst 3 1 2011 7 11
11. International Technology Roadmaps for Semiconductor (ITRS); 2010.
12. A. Chaudhry, and M.J. Kumar Investigation of the novel attributes of Na fully depleted dual-material gate SOI MOSFET IEEE Trans Electron Dev 51 9 2004 1463 1467
13. Integrated Systems Engineering (ISE) TCAD Manuals. Integrated Systems Engineering, Zurich, Switzerland; 2008 [release 10.0].
14. H. Lu, and Y. Taur An analytical potential model for symmetric and asymmetric DG MOSFETs IEEE Trans Electron Dev 53 5 2006 1161 1168
15. N. Mohan Kumar, Syamal Binit, and C.K. Sarkar Influence of channel and gate engineering on the analog and RF performance of DG MOSFETs IEEE Trans Electron Dev 57 4 2010 820 826
16. 2 gate dielectric Res Lett Phys 2008 1 5
17. J. Robertson High dielectric constant oxides Eur Phys J Appl Phys 28 3 2004 265 291 (Pubitemid 40002196)
18. C.R. Manoj, and V. Ramgopal Rao Impact of high k dielectrics on the device and circuit performance of nanoscale FinFETs IEEE Electron Dev Lett 28 4 2007 295 297
19. Nirmal D, Vijaya Kumar P, Samuel Patrick Chella, Shruti K, Thomas Divya Mary, Mohan Kumar P. Analysis of dual gate MOSFETs using high k dielectrics. In: Proceedings of the 3rd international conference on electronics computer technology, vol. 1, 2011. p. 22-5.