An ultra-low power asynchronous-logic in-situ self-adaptive VDD system for wireless sensor networks

IEEE Journal of Solid-State Circuits

Volumn 48, Issue 2, 2013, Pages 573-586

  Lin, Tong ^a   Chong, Kwen Siong ^a   Chang, Joseph S ^a   Gwee, Bah Hwee ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

Adaptive VDD scaling; asynchronous logic circuits; quasi delay insensitive circuits; sub threshold operation; ultra low power operation; wireless sensor networks

Indexed keywords

ADAPTIVE VDD SCALING; DESIGN APPROACHES; HIGH ROBUSTNESS; OPERATING CONDITION; POWER OPERATION; SELF-ADAPTIVE; SELF-TIMED; SUBTHRESHOLD; SUBTHRESHOLD OPERATION; ULTRA-LOW POWER;

ASYNCHRONOUS SEQUENTIAL LOGIC; DELAY CIRCUITS; FILTER BANKS; LOW POWER ELECTRONICS; THRESHOLD VOLTAGE; WIRELESS SENSOR NETWORKS;

LOGIC CIRCUITS;

EID: 84873310082     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2012.2223971     Document Type: Article

References (37)

1. G. Chen, S. Hanson, D. Blaauw, and D. Sylvester, "Circuit design advances for wireless sensing applications," in Proc. IEEE, Nov. 2010, vol. 98, no. 11, pp. 1808-1827.
2. M. Hempstead, D. Brooks, andG.-Y.Wei, "An accelerator-based wireless sensor network processor in 130 nm CMOS," IEEE JESTCAS, vol. 1, no. 2, pp. 193-202, Jun. 2011.
3. T. Reddy and D. Linden, Linden's Handbook of Batteries, 4th ed. : McGraw-Hill Professional, 2010.
4. Y. C. Lim, "Frequency response masking approach for the synthesis of sharp linear phase digital filters," IEEE Trans. Circuits and Systems, vol. 33, no. 4, pp. 357-364, Apr. 1986.
5. J. S. Chang and Y.-C. Tong, "A micropower-compatible time-multiplexed SC speech spectrum analyzer design," IEEE JSSC, vol. 28, no. 1, pp. 40-48, Jan. 1993.
6. L. S. Nielsen et al., "Low-power operation using self-timed circuits and adaptive scaling of the supply voltage," IEEE Trans. VLSI Syst., vol. 2, no. 4, pp. 391-397, Dec. 1994.
7. M. Nakai et al., "Dynamic voltage and frequency management for a low power embedded microprocessor," IEEE JSSC, vol. 40, no. 1, pp. 28-35, Jan. 2005.
8. A. Raychowdhury et al., "Computing with subthreshold leakage: Device/circuit/architecture co-design for ultralow-power subthreshold operation," IEEE Trans. VLSI Syst., vol. 13, pp. 1213-1224, Nov. 2005.
9. A. Wang, B. H. Calhoun, and A. P. Chandrakasan, Sub-Threshold Design for Ultra Low-Power Systems. : Springer, 2006.
10. K.-S. Chong, B.-H. Gwee, and J. S. Chang, "Energy-efficient synchronous-logic and asynchronous-logic FFT/IFFT processors," IEEE JSSC, vol. 42, no. 9, pp. 2034-2045, Sep. 2007. (Pubitemid 47331298)
11. S. Hanson et al., "Exploring variability and performance in a sub-200-mV processor," IEEE JSSC, vol. 43, no. 4, pp. 881-891, Apr. 2008.
12. E. Beigne et al., "An asynchronous power aware and adaptive NoC based circuit," IEEE JSSC, vol. 44, no. 4, pp. 1167-1177, Apr. 2009.
13. I. J. Chang, S. P. Park, and K. Roy, "Exploring asynchronous design techniques for process-tolerant and energy-efficient subthreshold operation," IEEE JSSC, vol. 45, no. 2, pp. 401-410, Feb. 2010.
14. R. D. Jorgenson et al., "Ultralow-power operation in subthreshold regimes applying clockless logic," in Proc. IEEE, Feb. 2010, vol. 98, no. 2, pp. 299-314.
15. K.-S. Chong et al., "Synchronous-logic and globally-asynchronous- locally-synchronous (GALS) acoustic digital signal processors," IEEE JSSC, vol. 47, no. 3, pp. 769-780, Mar. 2012.
16. A. J. Martin and M. Nsytrom, "Asynchronous techniques for system-on-chip designs," in Proc. IEEE, Jun. 2006, vol. 96, no. 6, pp. 1104-1115.
17. J. S. Chang, B.-H. Gwee, and K.-S. Chong, "Asynchronous-Logic for Full Dynamic Voltage Scaling," US Provisional Patent Application No. 61/364,478, Jul. 15, 2010.
18. J. S. Chang, Digital Asynchronous-Logic: Dynamic Voltage Control Final Technical Report for DARPA Project, HR0011-09-2-0006, Aug. 2010, et al.
19. J. Kwong et al., "A 65 nm sub-Vt microcontroller with integrated SRAM and switched-capacitor DC-DC converter," IEEE JSSC, vol. 44, no. 1, pp. 115-126, Jan. 2009.
20. D. N. Truong et al., "A 167-processor computational platform in 65 nm CMOS," IEEE JSSC, vol. 44, no. 4, pp. 1130-1144, Apr. 2009.
21. J. Tschanz et al., "Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging," in Proc. IEEE ISSCC, Feb. 2007, pp. 292-293.
22. J. Kao, M. Miyazaki, and A. Chandrakasan, "A 175-mV multiply-accumulate unit using an adaptive supply voltage and body bias architecture," IEEE JSSC, vol. 37, no. 11, pp. 1545-1554, Nov. 2002. (Pubitemid 35432177)
23. B. H. Calhoun and A. P. Chandrakasan, "Ultra-dynamic voltage scaling (UDVS) using sub-threshold operation and local voltage dithering," IEEE JSSC, vol. 41, pp. 238-245, Jan. 2006. (Pubitemid 43145981)
24. M. Elgebaly and M. Sachdev, "Variation-aware adaptive voltage scaling system," IEEE Trans. VLSI Syst., vol. 15, no. 5, pp. 560-571, May 2007. (Pubitemid 46853323)
25. Y. Ramadass and A. Chandrakasan, "Minimum energy tracking loop with embedded DC-DC converter enabling ultra-low-voltage operation down to 250 mV in 65 nm CMOS," IEEE JSSC, vol. 43, pp. 256-265, Jan. 2008.
26. D. Bol et al., "A 25 MHz 7 ultra-low-voltage microcontroller SoC in 65 nm LP/GP CMOS for low-carbon wireless sensor nodes," in Proc. IEEE ISSCC, Feb. 2012, pp. 490-492.
27. S. Das et al., "A self-tuning DVS processor using delay-error detection and correction," IEEE JSSC, vol. 41, no. 4, pp. 792-804, Apr. 2006.
28. S. Das et al., "Razor II: In situ error detection and correction for PVT and SER tolerance," IEEE JSSC, vol. 44, no. 1, pp. 32-48, Jan. 2009.
29. K. A. Bowman et al., "A 45 nm resilient microprocessor core for dynamic variation tolerance," IEEE JSSC, vol. 46, no. 1, pp. 194-208, Jan. 2011.
30. J. Mäkipää et al., "Timing-error detection design considerations in subthreshold: An 8-bit microprocessor in 65 nm CMOS," J. Low Power Electron. Appl., vol. 2, no. 2, pp. 180-196, 2012.
31. O. C. Akgun, J. Rodrigues, and J. Sparsø, "Minimum-energy subthreshold self-timed circuits: Design methodology and a case study," in Proc. 16th ASYNC, 2010, pp. 41-51.
32. W.-C. Hsieh and W. Hwang, "Adaptive power control technique on power-gated circuitries," IEEE Trans. VLSI Syst., vol. 19, no. 7, pp. 1167-1180, Jul. 2011.
33. J. Sparsø, J. Staunstrup, and M. Dantzer-Sorensen, "Design of delay insensitive circuits using multi-ring structures," in Proc. European DAC, 1992, pp. 7-10.
34. A. Kondratyev and K. Lwin, "Design of asynchronous circuits using synchronous CAD tools," IEEE Design Test Comput., vol. 19, no. 4, pp. 107-117, 2002. (Pubitemid 34752091)
35. J. Cortadella et al., "Coping with the variability of combinational logic delays," in Proc. ICCD, Oct. 2004, pp. 505-508. (Pubitemid 40557154)
36. D. Bol, "Robust and energy-efficient ultra-low-voltage circuit design under timing constraints in 65/45 nm CMOS," J. Low Power Electron. Appl., vol. 1, no. 1, pp. 1-19, 2011.
37. D. Bol et al., "The detrimental impact of negative Celsius temperature on ultra-low-voltage CMOS logic," in Proc. ESSCIRC, Sep. 2010, pp. 522-525.