Timing-error detection design considerations in subthreshold: An 8-bit microprocessor in 65 nm CMOS

Journal of Low Power Electronics and Applications

Volumn 2, Issue 2, 2012, Pages 180-196

  Mäkipää, Jani ^a   Turnquist, Matthew J ^b   Laulainen, Erkka ^b   Koskinen, Lauri ^b  

^a VTT TECHNICAL RESEARCH CENTRE OF FINLAND   (Finland)

^b AALTO UNIVERSITY   (Finland)

Author keywords

Dynamic supply voltage; Dynamic voltage scaling; SCL; Subthreshold; Subthreshold sourcecoupled logic; Timing error detection; Ultra low power; Weak inversion

Indexed keywords

EID: 84871700697     PISSN: None     EISSN: 20799268     Source Type: Journal    
DOI: 10.3390/jlpea2020180     Document Type: Article

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