-
4
-
-
33751085924
-
Upper bounding fault coverage by structural analysis and signal monitoring
-
IEEE
-
V. Agrawal, S. Bose, and V. Gangaram. Upper bounding fault coverage by structural analysis and signal monitoring. In VLSI Test Symposium, 2006. Proceedings. 24th IEEE, pages 6-p. IEEE, 2006.
-
VLSI Test Symposium, 2006. Proceedings. 24th IEEE
, vol.2006
, pp. 6
-
-
Agrawal, V.1
Bose, S.2
Gangaram, V.3
-
7
-
-
0031380354
-
Pentium (r) pro processor design for test and debug
-
IEEE
-
A. Carbine and D. Feltham. Pentium (r) pro processor design for test and debug. In Test Conference, 1997. Proceedings., International, pages 294-303. IEEE, 1997.
-
Test Conference, 1997. Proceedings., International
, vol.1997
, pp. 294-303
-
-
Carbine, A.1
Feltham, D.2
-
8
-
-
84873209441
-
A statistical model for fault coverage analysis. In vlsi test symposium 1991
-
Digest of Papers, IEEE
-
C. Chen and N. Soong. A statistical model for fault coverage analysis. In VLSI Test Symposium, 1991.'Chip-to-System Test Concerns for the 90's', Digest of Papers, pages 227-232. IEEE.
-
Chip-to-System Test Concerns for the 90's'
, pp. 227-232
-
-
Chen, C.1
Soong, N.2
-
9
-
-
0026618763
-
Hardware acceleration alone will not make fault grading ulsi a reality
-
IEEE
-
G. Ganapathy and J. Abraham. Hardware acceleration alone will not make fault grading ulsi a reality. In Test Conference, 1991, Proceedings., International, page 848. IEEE, 1991.
-
Test Conference, 1991, Proceedings., International
, vol.1991
, pp. 848
-
-
Ganapathy, G.1
Abraham, J.2
-
10
-
-
0028748426
-
Facts: Fault coverage estimation by test vector sampling
-
IEEE
-
K. Heragu, V. Agrawal, and M. Bushnell. Facts: fault coverage estimation by test vector sampling. In VLSI Test Symposium, 1994. Proceedings., 12th IEEE, pages 266-271. IEEE, 1994.
-
(1994)
VLSI Test Symposium, 1994. Proceedings., 12th IEEE
, pp. 266-271
-
-
Heragu, K.1
Agrawal, V.2
Bushnell, M.3
-
13
-
-
0030389115
-
-
IEEE
-
S. Karthik, M. Aitken, L. Martin, S. Pappula, B. Stettler, P. Vishakantaiah, M. d'Abreu, and J. Abraham. Distributed mixed level logic and fault simulation on the pentium (r) pro microprocessor. pages 160-166. IEEE, 1996.
-
(1996)
Distributed mixed level logic and fault simulation on the pentium (r) pro microprocessor.
, pp. 160-166
-
-
Karthik, S.1
Aitken, M.2
Martin, L.3
Pappula, S.4
Stettler, B.5
Vishakantaiah, P.6
D'Abreu, M.7
Abraham, J.8
-
14
-
-
0033361730
-
Fault coverage estimation for early stage of vlsi design
-
IEEE
-
V. Kim, T. Chen, and M. Tegethoff. Fault coverage estimation for early stage of vlsi design. In VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on, pages 105-108. IEEE, 1999.
-
VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on
, vol.1999
, pp. 105-108
-
-
Kim, V.1
Chen, T.2
Tegethoff, M.3
-
18
-
-
0027271157
-
Fast hierarchical multi-level fault simulation of sequential circuits with switch level accuracy
-
W. Meyer and R. Camposano. Fast hierarchical multi-level fault simulation of sequential circuits with switch-level accuracy. In Proceedings of the 30th international Design Automation Conference, pages 515-519. ACM, 1993. (Pubitemid 23673211)
-
(1993)
Proceedings - Design Automation Conference
, pp. 515-519
-
-
Meyer Wolfgang1
Camposano Raul2
-
20
-
-
0026819183
-
-
IEEE
-
T. Niermann, W. Cheng, and J. Patel. Proofs: A fast, memory-efficient sequential circuit fault simulator. volume 11, pages 198-207. IEEE, 1992.
-
(1992)
Proofs: A fast, memory-efficient sequential circuit fault simulator.
, vol.11
, pp. 198-207
-
-
Niermann, T.1
Cheng, W.2
Patel, J.3
-
21
-
-
84873176599
-
-
U. Of Illinois At Urbana-Champaign
-
U. of Illinois at Urbana-Champaign. Ivm processor. http://www.crhc. illinois.edu/ACS/tools/ivm/about.html.
-
Ivm Processor
-
-
-
22
-
-
84873145590
-
-
OpenCores. Opencores webpage.
-
OpenCores. Opencores webpage. http://opencores.org/openrisc,or1200.
-
-
-
-
24
-
-
3142657469
-
A statistical fault coverage metric for realistic path delay faults
-
IEEE
-
W. Qiu, X. Lu, J. Wang, Z. Li, D. Walker, and W. Shi. A statistical fault coverage metric for realistic path delay faults. In VLSI Test Symposium, 2004. Proceedings. 22nd IEEE, pages 37-42. IEEE, 2004.
-
VLSI Test Symposium, 2004. Proceedings. 22nd IEEE
, vol.2004
, pp. 37-42
-
-
Qiu, W.1
Lu, X.2
Wang, J.3
Li, Z.4
Walker, D.5
Lindsay, W.6
-
26
-
-
0029510552
-
A stafan-like functional testability measure for register-level circuits
-
IEEE
-
C. Ravikumar, G. Saund, and N. Agrawal. A stafan-like functional testability measure for register-level circuits. In Test Symposium, 1995., Proceedings of the Fourth Asian, pages 192-198. IEEE, 1995.
-
Test Symposium, 1995., Proceedings of the Fourth Asian
, vol.1995
, pp. 192-198
-
-
Ravikumar, C.1
Saund, G.2
Agrawal, N.3
-
27
-
-
27644480362
-
-
Springer
-
D. Saab, R. Mueller-Thuns, D. Blaauw, J. Rahmeh, and J. Abraham. Hierarchical multi-level fault simulation of large systems. volume 1, pages 139-149. Springer, 1990.
-
(1990)
Hierarchical multi-level fault simulation of large systems.
, vol.1
, pp. 139-149
-
-
Saab, D.1
Mueller-Thuns, R.2
Blaauw, D.3
Rahmeh, J.4
Abraham, J.5
-
29
-
-
0034484424
-
Register-transfer level fault modeling and test evaluation techniques for vlsi circuits
-
P. Thaker, V. Agrawal, and M. Zaghloul. Register-transfer level fault modeling and test evaluation techniques for vlsi circuits. International Test Conference, 2000.
-
(2000)
International Test Conference
-
-
Thaker, P.1
Agrawal, V.2
Zaghloul, M.3
-
31
-
-
0029546819
-
Emulating static faults using a xilinx based emulator
-
Published by the IEEE Computer Society
-
R. Wieler, Z. Zhang, and R. McLeod. Emulating static faults using a xilinx based emulator. In fccm, page 0110. Published by the IEEE Computer Society, 1995.
-
(1995)
Fccm
, pp. 0110
-
-
Wieler, R.1
Zhang, Z.2
McLeod, R.3
|