STAFAN-like functional testability measure for register-level circuits

Proceedings of the Asian Test Symposium

Volumn , Issue , 1995, Pages 192-198

  Ravikumar, C P ^a   Saund, Gurjeet S ^a   Agrawal, Nitin ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; COMPUTER SIMULATION; COMPUTER WORKSTATIONS; FAILURE ANALYSIS; LOGIC DEVICES; LOGIC GATES; MULTIPLYING CIRCUITS; STATISTICAL METHODS;

FAULT SIMULATION; GATE LEVEL DIGITAL CIRCUITS; REGISTER LEVEL CIRCUITS; STATISTICAL FAULT ANALYSIS; STUCK AT FAULT MODEL; TESTABILITY ANALYSIS ALGORITHM; TESTABILITY DRIVEN SYNTHESIS;

DIGITAL CIRCUITS;

EID: 0029510552     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)