Estimating stuck fault coverage in sequential logic using state traversal and entropy analysis

Proceedings - International Test Conference

Volumn , Issue , 2007, Pages

  Bose, Soumitra ^a,c   Agrawal, Vishwani D ^b  

^a INTEL CORPORATION   (United States)

^b AUBURN UNIVERSITY   (United States)

^c UBS Investment Bank   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN FOR TESTABILITY; MATHEMATICAL MODELS; PROBLEM SOLVING; STACKING FAULTS; VECTORS;

ENTROPY ANALYSIS; STATE TRAVERSAL ANALYSIS;

LOGIC CIRCUITS;

EID: 39749139584     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2007.4437635     Document Type: Conference Paper

References (15)