Fault coverage estimation for early stage of VLSI design

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 1999, Pages 105-108

  Kim, Von Kyoung ^a   Chen, Tom ^a   Tegethoff, Mick ^a  

^a SUN MICROSYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; DESIGN FOR TESTABILITY; FUNCTIONS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; PARAMETER ESTIMATION; SEQUENTIAL CIRCUITS;

EXPONENTIAL DECAY FUNCTION; FAULT COVERAGE ESTIMATION;

VLSI CIRCUITS;

EID: 0033361730     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)