A statistical fault coverage metric for realistic path delay faults

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2004, Pages 37-42

  Qiu, Wangqi ^a   Lu, Xiang ^a   Wang, Jing ^a   Li, Zhuo ^a   Walker, D M H ^a   Shi, Weiping ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY FAULTS; FAULT COVERAGES; FAULT DETECTION; TRANSITION FAULT MODELS;

DEFECTS; DELAY CIRCUITS; DESIGN FOR TESTABILITY; MATHEMATICAL MODELS; PROBABILITY DISTRIBUTIONS; PROBLEM SOLVING; QUALITY CONTROL; ROBUSTNESS (CONTROL SYSTEMS); STATISTICAL METHODS;

ELECTRON DEVICE TESTING;

EID: 3142657469     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (27)

1. Z. Barzilai and B. K. Rosen, "Comparison of AC Self-Testing Procedures," IEEE Int'l Test Conf., Philadelphia, PA, Oct. 1983, pp. 89-94.
2. J. L. Carter, V. S. Iyengar and B. K. Rosen, "Efficient Test Coverage Determination for Delay Faults," IEEE Int'l Test Conf., Washington, DC, Sept. 1987, pp. 418-427.
3. G. L. Smith, "Model for Delay Faults Based Upon Paths," IEEE Int'l Test Conf., Philadelphia, PA, Oct. 1985, pp. 342-349.
4. K. Heragu, V. D. Agrawal and M. L. Bushnell, "Statistical Methods for Delay Fault Coverage Analysis," VLSI Design Conf., New Delhi, India, Jan. 1995, pp. 166-170.
5. V. Iyengar, B. K. Rosen and I. Spillinger, "Delay Test Generation 1 - Concepts and Coverage Metrics," IEEE Int'l Test Conf., Washington, DC, Sept. 1988, pp. 857-866.
6. J. Waicukauski, E. Lindbloom, B. K. Rosen and V. S. Iyengar, "Transition Fault Simulation," IEEE Design & Test of Computers, vol. 4, no. 5, Apr. 1987, pp. 32-38.
7. T. W. Williams, B. Underwood and M. R. Mercer, "The Interdependence Between Delay-Optimization of Synthesized Networks and Testing," ACM/IEEE Design Automation Conf., San Francisco, CA, June 1991, pp. 87-92.
8. G. M. Luong and D. M. H. Walker, "Test Generation for Global Delay Faults," IEEE Int'l Test Conf., Washington, DC, Oct. 1996, pp. 433-442.
9. W. Maly, "Computer-Aided Design for VLSI Circuit Manufacturability," Proc. of the IEEE, vol. 78, no. 2, Feb. 1990, pp. 356-392.
10. D. M. H. Walker, "Tolerance of Delay Faults," IEEE Int'l Workshop on Defect and Fault Tolerance in VLSI Systems, Dallas, TX, Nov. 1992, pp. 207-216.
11. M. Sivaraman and A. J. Strojwas, "Delay Fault Coverage: A Realistic Metric and an Estimation Technique for Distributed Path Delay Faults," IEEE/ACM Int'l Conf. on Computer Aided Design, San Jose, CA, Nov. 1996, pp. 494-501.
12. J. J. Liou, L. C. Wang and K. T. Cheng, "On Theoretical and Practical Considerations of Path Selection for Delay Fault Testing," IEEE/ACM Int'l Conf. on Computer Aided Design, San Jose, CA, Nov. 2002, pp. 94-100.
13. A. K. Majhi, V. D. Agrawal, J. Jacob and L. M. Patnaik, "Line Coverage of Path Delay Faults," IEEE Trans. on VLSI Systems, vol. 8, no. 5, Oct. 2000, pp. 610-613.
14. A. Murakami, S. Kajihara, T. Sasao, I. Pomeranz and S. M. Reddy, "Selection of Potentially Testable Path Delay Faults for Test Generation," IEEE Int'l Test Conf., Atlantic City, NJ, Oct. 2000, pp. 376-384.
15. M. Sharma and J. H. Patel, "Finding a Small Set of Longest Testable Paths that Cover Every Gate," IEEE Int'l Test Conf., Baltimore, MD, Oct. 2002, pp. 974-982.
16. C. J. Lin and S. M. Reddy, "On Delay Fault Testing in Logic Circuits," IEEE Trans. on Computer-Aided Design, vol. 6, no. 5, Sept. 1987, pp. 694-703.
17. K. T. Cheng and H. C. Chen, "Classification and Identification of Non-Robust Untestable Path Delay Faults," IEEE Trans. on Computer-Aided Design, vol. 15, no. 8, Aug. 1996, pp. 845-853.
18. K. T. Cheng and H. C. Chen, "Delay Testing for Non-Robust Untestable Circuits," IEEE Int'l Test Conf., Baltimore, MD, Oct. 1993, pp. 954-961.
19. W. K. C. Lam, A. Saldanha, R. K. Brayton and A. L. Sangiovanni- Vincentelli, "Delay Fault Coverage and Performance Trade-Offs," ACM/IEEE Design Automation Conf., Dallas, TX, June 1993, pp. 446-452.
20. K. Fuchs, M. Pabst and T. Rossel, "RESIST: A Recursive Test Pattern Generation Algorithm for Path Delay Faults Considering Various Test Classes," IEEE Trans. on Computer-Aided Design, vol. 13, no. 12, Dec. 1994, pp. 1550-1562.
21. J. B. Brockman and S. W. Director, "Predictive Subset Testing: Optimizing IC Parametric Performance Testing for Quality, Cost, and Yield," IEEE Trans. on Semiconductor Manufacturing, vol. 2, no.3, Aug. 1989, pp. 104-113.
22. X. Lu, Z. Li, W. Qiu, W. Shi and D. M. H. Walker, "Longest Path Selection for Delay Test Under Process Variation," Asian and South Pacific Design Automation Conf., Yokohama, Japan, Jan. 2004, pp. 98-103.
23. V. R. Sar-Dessai and D. M. H. Walker, "Resistive Bridge Fault Modeling, Simulation and Test Generation," IEEE Int'l Test Conf., Atlantic City, NJ, Sept. 1999, pp. 596-605.
24. R. R. Montanes and J. P. Gyvez, "Resistance Characterization for Weak Open Defects," IEEE Trans. on Design & Test of Computers, vol. 19, no. 5, Sept.-Oct. 2002, pp. 18-25.
25. Z. Li, X. Lu, W. Qiu, W. Shi and D. M. H. Walker, "A Circuit Level Fault Model for Resistive Opens and Bridges," IEEE VLSI Test Symp., Napa Valley, CA, Apr. 2003, pp. 379-384.
26. W. Qiu and D. M. H. Walker, "An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit," IEEE Int'l Test Conf, Charlotte, NC, Sept. 2003, pp. 592-601.
27. D. Belete, A. Razdan, W. Schwarz, R. Raina, C. Hawkins and J. Morehead, "Use of DFT Techniques in Speed Grading a 1GHz+ Microprocessor," IEEE Int'l Test Conf., Baltimore, MD, Oct. 2002, pp. 1111-1119.