Upper bounding fault coverage by structural analysis and signal monitoring

Proceedings of the IEEE VLSI Test Symposium

Volumn 2006, Issue , 2006, Pages 88-93

  Agrawal, Vishwani D ^a   Bose, Soumitra ^b   Gangaram, Vijay ^b  

^a AUBURN UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT GRAPH; INPUT SEQUENCE; LOGIC SIMULATOR; STUCK-FAULT COVERAGE ESTIMATOR;

ALGORITHMS; COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; MATHEMATICAL MODELS; PARAMETER ESTIMATION; SIGNAL PROCESSING;

ELECTRIC FAULT CURRENTS;

EID: 33751085924     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2006.89     Document Type: Conference Paper

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