Register-transfer level fault modeling and test evaluation techniques for VLSI circuits

IEEE International Test Conference (TC)

Volumn , Issue , 2000, Pages 940-949

  Thaker, Pradip A ^a   Agrawal, Vishwani D ^a   Zaghloul, Mona E ^a  

^a HUGHES NETWORK SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; DESIGN FOR TESTABILITY; FAILURE ANALYSIS; LOGIC GATES; MICROCONTROLLERS; STATIC RANDOM ACCESS STORAGE; VLSI CIRCUITS;

FAULT INJECTION ALGORITHM; REGISTER TRANSFER LEVEL FAULT MODELING; VERILOG HARDWARE DESCRIPTION LANGUAGE;

INTEGRATED CIRCUIT TESTING;

EID: 0034484424     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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