-
1
-
-
80052647818
-
Measurement, analysis and improvement of supply noise in 3D ICs
-
P. Jain, D. Jiao, X. Wang, and C. H. Kim, "Measurement, analysis and improvement of supply noise in 3D ICs," in Proc. Symp. VLSI Circuits, 2011, pp. 46-47.
-
(2011)
Proc. Symp. VLSI Circuits
, pp. 46-47
-
-
Jain, P.1
Jiao, D.2
Wang, X.3
Kim, C.H.4
-
2
-
-
0033670992
-
Model and analysis for combined package and on-chip power grid simulation
-
R. Panda, D. Blaauw, R. Chaudhry, V. Zolotov, B. Young, and R. Ra-maraju, "Model and analysis for combined package and on-chip power grid simulation," in Proc. IEEE Int. Symp. Low Power Electron. Design, 2000, pp. 179-184.
-
(2000)
Proc. IEEE Int. Symp. Low Power Electron. Design
, pp. 179-184
-
-
Panda, R.1
Blaauw, D.2
Chaudhry, R.3
Zolotov, V.4
Young, B.5
Ra-Maraju, R.6
-
3
-
-
34547323629
-
Power grid physics and implications for CAD
-
DOI 10.1145/1146909.1146964, 2006 43rd ACM/IEEE Design Automation Conference, DAC'06
-
S. Pant and E. Chiprout, "Power grid physics and implications for CAD," in Proc. ACM/IEEE Design Autom. Conf., 2006, pp. 199-204. (Pubitemid 47129491)
-
(2006)
Proceedings - Design Automation Conference
, pp. 199-204
-
-
Pant, S.1
Chiprout, E.2
-
4
-
-
47949124019
-
Power delivery for 3D chip stacks: Physical modeling and design implication
-
G. Huang, M. Bakir, A. Naeemi, H. Chen, and J. D. Meindl, "Power delivery for 3D chip stacks: Physical modeling and design implication," in Proc. IEEE Elect. Perform. Electron. Packag., 2007, pp. 205-208.
-
(2007)
Proc. IEEE Elect. Perform. Electron. Packag.
, pp. 205-208
-
-
Huang, G.1
Bakir, M.2
Naeemi, A.3
Chen, H.4
Meindl, J.D.5
-
5
-
-
58049122127
-
3D power distribution network co-design for nanoscale stacked silicon IC
-
A. Shayan, X. Hu, H. Peng, W. Zhang, C. K. Cheng, M. Popovich, and X. Chen, "3D power distribution network co-design for nanoscale stacked silicon IC," in Proc. IEEE Elect. Perform. Electron. Packag., 2008, pp. 11-14.
-
(2008)
Proc. IEEE Elect. Perform. Electron. Packag.
, pp. 11-14
-
-
Shayan, A.1
Hu, X.2
Peng, H.3
Zhang, W.4
Cheng, C.K.5
Popovich, M.6
Chen, X.7
-
6
-
-
0033343078
-
Power distribution system design methodology and capacitor selection for modern CMOS technology
-
DOI 10.1109/6040.784476
-
L. D. Smith, R. E. Anderson, D. W. Forehand, T. J. Pelc, and T. Roy, "Power distribution system design methodology and capacitor selection for modern CMOS technology," IEEE Trans. Adv. Packag., vol. 22, no. 3, pp. 284-291, Aug. 1999. (Pubitemid 30559648)
-
(1999)
IEEE Transactions on Advanced Packaging
, vol.22
, Issue.3
, pp. 284-291
-
-
Smith, L.D.1
Anderson, R.E.2
Forehand, D.W.3
Pelc, T.J.4
Roy, T.5
-
7
-
-
0042591349
-
A static pattern-independent technique for power grid voltage integrity verification
-
D. Kouroussis and F. N. Najm, "A static pattern-independent technique for power grid voltage integrity verification," in Proc. ACM/IEEE Design Autom. Conf., 2003, pp. 99-104.
-
(2003)
Proc. ACM/IEEE Design Autom. Conf.
, pp. 99-104
-
-
Kouroussis, D.1
Najm, F.N.2
-
8
-
-
70350724699
-
Fast vectorless power grid verification using an approximate inverse technique
-
N. H. A. Ghani and F. N. Najm, "Fast vectorless power grid verification using an approximate inverse technique," in Proc. ACM/IEEE Design Autom. Conf., 2009, pp. 184-189.
-
(2009)
Proc. ACM/IEEE Design Autom. Conf.
, pp. 184-189
-
-
Ghani, N.H.A.1
Najm, F.N.2
-
9
-
-
77950807406
-
On the bound of time-domain power supply noise based on frequency-domain target impedance
-
X. Hu, W. Zhao, Y. Zhang, A. Shayan, C. Pan, A. E. Engin, and C. K. Cheng, "On the bound of time-domain power supply noise based on frequency-domain target impedance," in Proc. Syst. Level Interconnect Prediction Workshop, 2009, pp. 69-76.
-
(2009)
Proc. Syst. Level Interconnect Prediction Workshop
, pp. 69-76
-
-
Hu, X.1
Zhao, W.2
Zhang, Y.3
Shayan, A.4
Pan, C.5
Engin, A.E.6
Cheng, C.K.7
-
10
-
-
77952613906
-
Worst-case noise prediction with non-zero current transition times for early power distribution system verification
-
P. Du, X. Hu, S. H. Weng, A. Shayan, X. Chen, A. E. Engin, and C. K. Cheng, "Worst-case noise prediction with non-zero current transition times for early power distribution system verification," in Proc. IEEE Int. Symp. Quality Electron. Design, 2010, pp. 624-631.
-
(2010)
Proc. IEEE Int. Symp. Quality Electron. Design
, pp. 624-631
-
-
Du, P.1
Hu, X.2
Weng, S.H.3
Shayan, A.4
Chen, X.5
Engin, A.E.6
Cheng, C.K.7
-
12
-
-
58849138950
-
Wafer-level assembly of heterogeneous technologies
-
J. Q. Lu, A. Jindal, P. D. Persans, and R. J. Gutmann, "Wafer-level assembly of heterogeneous technologies," in Proc. Int. Conf. Semicond. Manuf. Technol., 2003, pp. 91-94.
-
(2003)
Proc. Int. Conf. Semicond. Manuf. Technol.
, pp. 91-94
-
-
Lu, J.Q.1
Jindal, A.2
Persans, P.D.3
Gutmann, R.J.4
-
13
-
-
0036999740
-
Inductive properties of high-performance power distributions grids
-
Dec.
-
A. V. Mezhiba and E. G. Friedman, "Inductive properties of high-performance power distributions grids," IEEE Trans. Very Large Scale In-tegr. (VLSI) Syst., vol. 10, no. 6, pp. 762-776, Dec. 2002.
-
(2002)
IEEE Trans. Very Large Scale In-tegr. (VLSI) Syst.
, vol.10
, Issue.6
, pp. 762-776
-
-
Mezhiba, A.V.1
Friedman, E.G.2
-
15
-
-
61649110276
-
Three-dimensional silicon integration
-
J. U. Knickerbocker, P. S. Andry, B. Dang, R. R. Horton, M. J. Interrante, C. S. Patel, R. J. Polastre, K. Sakuma, R. Sirdeshmukh, E. J. Sprogis, S. M. Sri-Jayantha, A. M. Stephens, A. W. Topol, C. K. Tsang, B. C. Webb, and S. L. Wright, "Three-dimensional silicon integration," IBM J. Res. Develop., vol. 52, pp. 553-569, 2008.
-
(2008)
IBM J. Res. Develop.
, vol.52
, pp. 553-569
-
-
Knickerbocker, J.U.1
Andry, P.S.2
Dang, B.3
Horton, R.R.4
Interrante, M.J.5
Patel, C.S.6
Polastre, R.J.7
Sakuma, K.8
Sirdeshmukh, R.9
Sprogis, E.J.10
Sri-Jayantha, S.M.11
Stephens, A.M.12
Topol, A.W.13
Tsang, C.K.14
Webb, B.C.15
Wright, S.L.16
-
16
-
-
73349133689
-
Electrical modeling and characterization of through silicon via for three-dimensional ICs
-
Jan.
-
G. Katti, M. Stucchi, K. D. Meyer, and W. Dehaene, "Electrical modeling and characterization of through silicon via for three-dimensional ICs," IEEE Trans. Electron Devices, vol. 57, no. 1, pp. 256-262, Jan. 2010.
-
(2010)
IEEE Trans. Electron Devices
, vol.57
, Issue.1
, pp. 256-262
-
-
Katti, G.1
Stucchi, M.2
Meyer, K.D.3
Dehaene, W.4
-
17
-
-
58049093383
-
Chip-package co-design methodology for global co-simulation of re-distribution layers (RDL)
-
S. Wane and A.-Y. Kuo, "Chip-package co-design methodology for global co-simulation of re-distribution layers (RDL)," in Proc. IEEE Elect. Perform. Electron. Packag., 2008, pp. 59-62.
-
(2008)
Proc. IEEE Elect. Perform. Electron. Packag.
, pp. 59-62
-
-
Wane, S.1
Kuo, A.-Y.2
-
18
-
-
67649662615
-
Parallel flow to analyze the impact of the voltage regulator model in nanoscale power distribution network
-
A. Shayan, X. Hu, H. Peng, W. Zhang, and C. K. Cheng, "Parallel flow to analyze the impact of the voltage regulator model in nanoscale power distribution network," in Proc. 10th Int. Symp. Quality Electron. Design, 2009, pp. 576-581.
-
(2009)
Proc. 10th Int. Symp. Quality Electron. Design
, pp. 576-581
-
-
Shayan, A.1
Hu, X.2
Peng, H.3
Zhang, W.4
Cheng, C.K.5
-
19
-
-
84872848397
-
-
A. Shayan, X. Hu, H. Peng, W. Zhang, and C. K. Cheng, "HFSS simulator," 2011. [Online]. Available: http://www.ansoft.com/products/hf/ hfss
-
(2011)
HFSS Simulator
-
-
Shayan, A.1
Hu, X.2
Peng, H.3
Zhang, W.4
Cheng, C.K.5
-
20
-
-
84872877063
-
-
A. Shayan, X. Hu, H. Peng, W. Zhang, and C. K. Cheng, "Sigrity XcitePI," 2011. [Online]. Available: http://www.sigrity.com/products/ xcitepi/xcitepi.htm
-
(2011)
Sigrity XcitePI
-
-
Shayan, A.1
Hu, X.2
Peng, H.3
Zhang, W.4
Cheng, C.K.5
-
21
-
-
84872876427
-
-
A. Shayan, X. Hu, H. Peng, W. Zhang, and C. K. Cheng, "Apache red-hawk," 2011. [Online]. Available: http://www.apache-da.com/prod-ucts/ redhawk
-
(2011)
Apache Red-hawk
-
-
Shayan, A.1
Hu, X.2
Peng, H.3
Zhang, W.4
Cheng, C.K.5
-
22
-
-
79955976791
-
Enabling power distribution network analysis flows for 3D ICs
-
X. Hu, T. Toms, R. Radojcic, M. Nowak, N. Yu, and C. K. Cheng, "Enabling power distribution network analysis flows for 3D ICs," in Proc. IEEE Int. 3D Syst. Integr. Conf., 2010, pp. 1-4.
-
(2010)
Proc. IEEE Int. 3D Syst. Integr. Conf.
, pp. 1-4
-
-
Hu, X.1
Toms, T.2
Radojcic, R.3
Nowak, M.4
Yu, N.5
Cheng, C.K.6
-
23
-
-
78650933951
-
Exploring the rogue wave phenomenon in 3D power distribution networks
-
X. Hu, P. Du, and C. K. Cheng, "Exploring the rogue wave phenomenon in 3D power distribution networks," in Proc. IEEE 19th Conf. Elect. Perform. Electron. Packag. Syst., 2010, pp. 57-60.
-
(2010)
Proc. IEEE 19th Conf. Elect. Perform. Electron. Packag. Syst.
, pp. 57-60
-
-
Hu, X.1
Du, P.2
Cheng, C.K.3
-
24
-
-
47949116921
-
Chip power model-A new methodology for system power integrity analysis and design
-
E. Kulali, E. Wasserman, and J. Zheng, "Chip power model-A new methodology for system power integrity analysis and design," IEEE Elect. Perform. Electron. Packag., pp. 259-262, 2007.
-
(2007)
IEEE Elect. Perform. Electron. Packag.
, pp. 259-262
-
-
Kulali, E.1
Wasserman, E.2
Zheng, J.3
-
25
-
-
29144439210
-
Effects of on-chip inductance on power distribution grid
-
Proceedings of ISPD'05 - 2005 International Symposium on Physical Design
-
A. Muramatsu, M. Hashimoto, and H. Onodera, "Effects of on-chip inductance on power distribution grid," in Proc. IEEE Int. Symp. Phys. Design, 2005, pp. 63-69. (Pubitemid 41816845)
-
(2005)
Proceedings of the International Symposium on Physical Design
, pp. 63-69
-
-
Muramatsu, A.1
Hashimoto, M.2
Onodera, H.3
-
26
-
-
77951244578
-
An adaptive parallel flow for power distribution network simulation using discrete fourier transform
-
X. Hu, W. Zhao, P. Du, A. Shayan, and C. K. Cheng, "An adaptive parallel flow for power distribution network simulation using discrete fourier transform," in Proc. IEEE Asia South Pacific Design Autom. Conf., 2010, pp. 125-130.
-
(2010)
Proc. IEEE Asia South Pacific Design Autom. Conf.
, pp. 125-130
-
-
Hu, X.1
Zhao, W.2
Du, P.3
Shayan, A.4
Cheng, C.K.5
|