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Volumn 21, Issue 2, 2013, Pages 354-366

Modeling and analysis of power distribution networks in 3-D ICs

Author keywords

3 D IC; modeling and analysis; power distribution network

Indexed keywords

3-D ICS; DISTRIBUTED MODELS; ELECTRICAL CHARACTERISTIC; FREQUENCY DOMAINS; GLOBAL EFFECTS; LOCAL RESONANCE; LUMPED MODELS; METAL LAYER; MODELING AND ANALYSIS; NOISE BEHAVIOR; ON CHIPS; PHYSICAL MECHANISM; POWER DISTRIBUTION NETWORK; POWER GRIDS; RESONANCE PHENOMENA; ROGUE WAVES; SUPPLY NOISE; TEMPORAL RELATION; TIME DOMAIN;

EID: 84872862469     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2012.2183904     Document Type: Article
Times cited : (8)

References (26)
  • 1
    • 80052647818 scopus 로고    scopus 로고
    • Measurement, analysis and improvement of supply noise in 3D ICs
    • P. Jain, D. Jiao, X. Wang, and C. H. Kim, "Measurement, analysis and improvement of supply noise in 3D ICs," in Proc. Symp. VLSI Circuits, 2011, pp. 46-47.
    • (2011) Proc. Symp. VLSI Circuits , pp. 46-47
    • Jain, P.1    Jiao, D.2    Wang, X.3    Kim, C.H.4
  • 3
    • 34547323629 scopus 로고    scopus 로고
    • Power grid physics and implications for CAD
    • DOI 10.1145/1146909.1146964, 2006 43rd ACM/IEEE Design Automation Conference, DAC'06
    • S. Pant and E. Chiprout, "Power grid physics and implications for CAD," in Proc. ACM/IEEE Design Autom. Conf., 2006, pp. 199-204. (Pubitemid 47129491)
    • (2006) Proceedings - Design Automation Conference , pp. 199-204
    • Pant, S.1    Chiprout, E.2
  • 6
    • 0033343078 scopus 로고    scopus 로고
    • Power distribution system design methodology and capacitor selection for modern CMOS technology
    • DOI 10.1109/6040.784476
    • L. D. Smith, R. E. Anderson, D. W. Forehand, T. J. Pelc, and T. Roy, "Power distribution system design methodology and capacitor selection for modern CMOS technology," IEEE Trans. Adv. Packag., vol. 22, no. 3, pp. 284-291, Aug. 1999. (Pubitemid 30559648)
    • (1999) IEEE Transactions on Advanced Packaging , vol.22 , Issue.3 , pp. 284-291
    • Smith, L.D.1    Anderson, R.E.2    Forehand, D.W.3    Pelc, T.J.4    Roy, T.5
  • 7
    • 0042591349 scopus 로고    scopus 로고
    • A static pattern-independent technique for power grid voltage integrity verification
    • D. Kouroussis and F. N. Najm, "A static pattern-independent technique for power grid voltage integrity verification," in Proc. ACM/IEEE Design Autom. Conf., 2003, pp. 99-104.
    • (2003) Proc. ACM/IEEE Design Autom. Conf. , pp. 99-104
    • Kouroussis, D.1    Najm, F.N.2
  • 8
    • 70350724699 scopus 로고    scopus 로고
    • Fast vectorless power grid verification using an approximate inverse technique
    • N. H. A. Ghani and F. N. Najm, "Fast vectorless power grid verification using an approximate inverse technique," in Proc. ACM/IEEE Design Autom. Conf., 2009, pp. 184-189.
    • (2009) Proc. ACM/IEEE Design Autom. Conf. , pp. 184-189
    • Ghani, N.H.A.1    Najm, F.N.2
  • 13
    • 0036999740 scopus 로고    scopus 로고
    • Inductive properties of high-performance power distributions grids
    • Dec.
    • A. V. Mezhiba and E. G. Friedman, "Inductive properties of high-performance power distributions grids," IEEE Trans. Very Large Scale In-tegr. (VLSI) Syst., vol. 10, no. 6, pp. 762-776, Dec. 2002.
    • (2002) IEEE Trans. Very Large Scale In-tegr. (VLSI) Syst. , vol.10 , Issue.6 , pp. 762-776
    • Mezhiba, A.V.1    Friedman, E.G.2
  • 16
    • 73349133689 scopus 로고    scopus 로고
    • Electrical modeling and characterization of through silicon via for three-dimensional ICs
    • Jan.
    • G. Katti, M. Stucchi, K. D. Meyer, and W. Dehaene, "Electrical modeling and characterization of through silicon via for three-dimensional ICs," IEEE Trans. Electron Devices, vol. 57, no. 1, pp. 256-262, Jan. 2010.
    • (2010) IEEE Trans. Electron Devices , vol.57 , Issue.1 , pp. 256-262
    • Katti, G.1    Stucchi, M.2    Meyer, K.D.3    Dehaene, W.4
  • 17
    • 58049093383 scopus 로고    scopus 로고
    • Chip-package co-design methodology for global co-simulation of re-distribution layers (RDL)
    • S. Wane and A.-Y. Kuo, "Chip-package co-design methodology for global co-simulation of re-distribution layers (RDL)," in Proc. IEEE Elect. Perform. Electron. Packag., 2008, pp. 59-62.
    • (2008) Proc. IEEE Elect. Perform. Electron. Packag. , pp. 59-62
    • Wane, S.1    Kuo, A.-Y.2
  • 18
    • 67649662615 scopus 로고    scopus 로고
    • Parallel flow to analyze the impact of the voltage regulator model in nanoscale power distribution network
    • A. Shayan, X. Hu, H. Peng, W. Zhang, and C. K. Cheng, "Parallel flow to analyze the impact of the voltage regulator model in nanoscale power distribution network," in Proc. 10th Int. Symp. Quality Electron. Design, 2009, pp. 576-581.
    • (2009) Proc. 10th Int. Symp. Quality Electron. Design , pp. 576-581
    • Shayan, A.1    Hu, X.2    Peng, H.3    Zhang, W.4    Cheng, C.K.5
  • 24
    • 47949116921 scopus 로고    scopus 로고
    • Chip power model-A new methodology for system power integrity analysis and design
    • E. Kulali, E. Wasserman, and J. Zheng, "Chip power model-A new methodology for system power integrity analysis and design," IEEE Elect. Perform. Electron. Packag., pp. 259-262, 2007.
    • (2007) IEEE Elect. Perform. Electron. Packag. , pp. 259-262
    • Kulali, E.1    Wasserman, E.2    Zheng, J.3
  • 26
    • 77951244578 scopus 로고    scopus 로고
    • An adaptive parallel flow for power distribution network simulation using discrete fourier transform
    • X. Hu, W. Zhao, P. Du, A. Shayan, and C. K. Cheng, "An adaptive parallel flow for power distribution network simulation using discrete fourier transform," in Proc. IEEE Asia South Pacific Design Autom. Conf., 2010, pp. 125-130.
    • (2010) Proc. IEEE Asia South Pacific Design Autom. Conf. , pp. 125-130
    • Hu, X.1    Zhao, W.2    Du, P.3    Shayan, A.4    Cheng, C.K.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.