Chip power model - A new methodology for system power integrity analysis and design

IEEE Topical Meeting on Electrical Performance of Electronic Packaging

Volumn , Issue , 2007, Pages 259-262

  Kulali, Emre ^a   Wasserman, Evgeny ^a   Zheng, Ji ^a  

^a Apache Design Solutions   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP POWERS; CO DESIGNS; COMPACT CHIPS; EQUIVALENT CIRCUIT MODELS; POWER INTEGRITIES;

ELECTRIC NETWORK ANALYSIS; ELECTRONIC EQUIPMENT MANUFACTURE; ELECTRONICS PACKAGING; SPICE;

CHIP SCALE PACKAGES;

EID: 47949116921     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEP.2007.4387176     Document Type: Conference Paper

References (6)

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2. E. J. Grimme, "Krylov projection methods for model reduction", Ph.D dissertation, Univ. Illinois, Urbana-Champaign, 1997
3. K. J. Kerns and A. T. Yang, "Preservation of passivity during RLC network reduction via split congruence transformations", IEEE Trans. Computer-Aided Design, vol. 17, no. 7, pp.582-591, July 1998
4. T. Palenius, "Efficient time-domain simulation of interconnects characterized by large RLC circuits or tabulated S-parameters", Ph.D dissertation, Helsinki University of Technology, 2004
5. B. Gustavsen and A. Semlyen, "Enforcing passivity for admittance matrices approximated by rational functions", IEEE Trans. Power Systems, vol. 16, no. 1, pp.97-104, Feb. 2001
6. S. Grivet-Talocia, "Passivity enforcement via perturbation of Hamiltonian matrices", IEEE Trans. Circuits and Systems -I, vol.51, no.9, pp. 1755-1769, Sept. 2004