A static pattern-independent technique for power grid voltage integrity verification

Proceedings - Design Automation Conference

Volumn , Issue , 2003, Pages 99-104

  Kouroussis, Dionysios ^a   Najm, Farid N ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

Algorithms; Design; Verification

Indexed keywords

CONSTRAINT THEORY; ELECTRIC POTENTIAL; ELECTRONICS PACKAGING; ERROR ANALYSIS; PROBLEM SOLVING;

VOLTAGE INTEGRITY VERIFICATION;

ELECTRIC NETWORK ANALYSIS;

EID: 0042591349     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/775859.775861     Document Type: Conference Paper

References (9)

1. th Design Automation Conference, San Francisco, 1998.
2. th Design Automation Conference, San Francisco, 1998.
3. th Design Automation Conference, 2000.
4. L. T. Pillage, R. A. Rohrer, and C. Visweswaraiah. Electronic Circuit and System Simulation Methods. McGraw-Hill, Inc., New York, NY, 1995.
5. G. H. Golub and C. F. Van Loan. Matrix Computations. The Johns Hopkins University Press, 1996.
6. A. Berman and R. J. Plemmons. Nonnegative Matrices in the Mathematical Science. Academic Press, New York, 1996.
7. H. Kriplani, F. N. Najm, and I. Hajj. Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: algorithms, signal correlations, and their resolution. IEEE Transactions on Computer-Aided Design, 14(8):998-1012, August 1995.
8. Jorge Rubenstein, Paul Penfield, and Mark A. Horowitz. Signal delay in RC tree networks. IEEE Trans. on Computer-Aided Design, 2(3):202-211, July 1983.
9. D. G. Luenberger. Linear and Nonlinear Programming. Addison-Wesley, Reading, MA, 2nd edition, 1984.