3D power distribution network co-design for nanoseale stacked silicon ICs

Electrical Performance of Electronic Packaging, EPEP

Volumn , Issue , 2008, Pages 11-14

  Shayan, Amirali ^a   Hu, Xiang ^b   Peng, He ^a   Popovich, Mikhail ^c   Zhang, Wanping ^a   Cheng, Chung Kuan ^a   Chua Eoan, Lew ^c   Chen, Xiaoming ^c  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c QUALCOMM INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CO DESIGNS; CPU TIMES; DESIGN PARAMETERS; FREQUENCY DOMAINS; ON CHIPS; PARALLEL COMPUTING; POWER DISTRIBUTION NETWORKS; SIMULATION TOOLS; SIMULTANEOUS SWITCHING NOISES; VOLTAGE REGULATOR MODULES;

CHIP SCALE PACKAGES; DISTRIBUTED PARAMETER NETWORKS; DISTRIBUTION OF GOODS; ELECTRIC NETWORK ANALYSIS; ELECTRIC POTENTIAL; ELECTRIC POWER DISTRIBUTION; ELECTRONIC EQUIPMENT MANUFACTURE; ELECTRONICS PACKAGING; FLOW SIMULATION; PARALLEL PROCESSING SYSTEMS; VOLTAGE REGULATORS;

THREE DIMENSIONAL;

EID: 58049122127     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEP.2008.4675863     Document Type: Conference Paper

References (5)

1. M. M. Budnik and K. Roy. A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale Technologies. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(12): 1336-1346, Dec. 2006.
2. G. Huang, M. Bakir, A. Naeemi, H. Chen, and J. D. Meindl. Power delivery for 3d chip stacks: Physical modeling and design implication. In IEEE Electrical Performance of Electronic Packaging, 2007, pages 205-208, Oct. 2007.
3. C. Ryu, D. Chung, J. Lee, K. Lee, T. Oh, and J. Kim. High Frequency Electrical Circuit Model of Chip-to-chip Vertical Via Interconnection for 3-D Chip Stacking Package. In IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging, 2005, pages 151-154, Oct. 2005.
4. J. Sun, J.-Q. Lu, D. Giuliano, T. P. Chow, and R. J. Gutmann. 3D Power Delivery for Microprocessors and High-Performance ASICs. In IEEE 22nd Applied Power Electronics Conference, 2007, pages 127-133, Mar. 2007.
5. W. Zhang, L. Zhang, R. Shi, H. Peng, Z. Zhu, L. Chua-Eoan, R. Murgai, T. Shibuya, N. Ito, and C. K. Cheng. Fast Power Network Analysis with Multiple Clock Domains. In 25th International Conference on Computer Design, 2007, pages 456-463, Oct. 2007.