An empirical approach to finding energy efficient ADC architectures

IMEKO TC4 International Workshop on ADC Modelling, Testing and Data Converter Analysis and Design 2011, IWADC 2011 and IEEE 2011 ADC Forum

Volumn , Issue , 2011, Pages 132-137

  Jonsson, Bengt E ^a  

^a ADMS Design AB ^*  (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN OPTIMIZATION; EMPIRICAL APPROACH; ENERGY EFFICIENT; LOW POWER; PERFORMANCE DATA; POWER EFFICIENCY;

DESIGN; ENERGY EFFICIENCY; OPTIMIZATION;

ARCHITECTURE;

EID: 84872587168     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (26)

1. F. Maloberti, F. Francesconi, P. Malcovati, and O. J. A. P. Nys, "Design considerations on low-voltage low-power data converters," IEEE Trans. Circuits and Systems, pt. I, vol. 42, no. 11, pp. 853-863, Nov. 1995.
2. P. B. Kenington, and L. Astier, "Power consumption of A/D converters for software radio applications". IEEE Trans. Vehicular Tech., vol. 49, no. 2, pp. 643-650, March 2000.
3. S. Kawahito, "Low-Power Design of Pipeline A/D Converters," Proc. of IEEE Custom Integrated Circ. Conf. (CICC), San Jose, California, USA, pp. 505-512, Sept., 2006.
4. C. Svensson, S. Andersson, and P. Bogner, "On the power consumption of analog to digital converters," Proc. of NORCHIP, Linköping, Sweden, pp. 49-52, Nov., 2006.
5. B. Bechen, T. v. d. Boom, D. Weiler, and B. J. Hosticka, "Theoretical and practical minimum of the power consumption of 3 ADCs in SC technique," Proc. of Eur. Conf. Circ. Theory and Design (ECCTD), Seville, Spain, pp. 444-447, Aug., 2007.
6. T. Sundström, B. Murmann, and C. Svensson, "Power dissipation bounds for high-speed Nyquist analog-to-digital converters," IEEE Trans. Circuits and Systems, pt. I, vol. 56, no. 3, pp. 509-518, Mar. 2009.
7. R. H. Walden, "Analog-to-digital converter survey and analysis," IEEE J. Selected Areas in Communications, no. 4, pp. 539-550, Apr. 1999.
8. K. G. Merkel, and A. L. Wilson, "A survey of high performance analog-to-digital converters for defense space applications," in Proc. IEEE Aerospace Conf., Big Sky, Montana, Mar. 2003, vol. 5, pp. 2415-2427.
9. B. Le, T. W. Rondeau, J. H. Reed, and C. W. Bostian, "Analog-to- digital converters [A review of the past, present, and future]," IEEE Signal Processing Magazine, pp. 69-77, Nov. 2005.
10. B. Murmann, "A/D converter trends: Power dissipation, scaling and digitally assisted architectures," Proc. of IEEE Custom Integrated Circ. Conf. (CICC), San Jose, California, USA, pp. 105-112, Sept., 2008.
11. B. E. Jonsson, "A survey of A/D-converter performance evolution," Proc. of IEEE Int. Conf. Electronics Circ. Syst. (ICECS), Athens, Greece, pp. 768-771, Dec., 2010.
12. B. E. Jonsson, "On CMOS scaling and A/D-converter performance," Proc. of NORCHIP, Tampere, Finland, pp. 1-4, Nov. 2010.
13. G. Van der Plas, S. Decoutere, and S. Donnay, "A 0.16pJ/conversion-step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS process," Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 2310-2312, Feb., 2006.
14. U. Wismar, D. Wisland, and P. Andreani, "A 0.2V 0.44μW 20 kHz analog to digital ΣΔ modulator with 57 fJ/conversion FoM," Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Montreux, Switzerland, pp. 187-190, Sept., 2006.
15. G. Van der Plas and B. Verbruggen, "A 150 MS/s 133 μW 7 bit ADC in 90 nm digital CMOS," IEEE J. Solid-State Circuits, Vol. 43, pp. 2631-2640, Dec., 2008.
16. B. Verbruggen, J. Craninckx, M. Kujik, P. Wambacq, and G. Van der Plas, "A 2.2mW 5b 1.75GS/s folding flash ADC in 90nm digital CMOS," Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 252-253, Feb., 2008.
17. B. Verbruggen, J. Craninckx, M. Kujik, P. Wambacq, and G. Van der Plas, "A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS," Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 296-297, Feb., 2010.
18. Y.-Z. Lin, S.-J. Chang, Y.-T. Liu, C.-C. Liu, and G.-Y. Huang, "A 5b 800MS/s 2mW Asynchronous Binary-Search ADC in 65nm CMOS," Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 80-81, Feb., 2009.
19. M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, "A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s charge-redistribution ADC," Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 244-245, Feb., 2008.
20. S. Pavan, N. Krishnapura, R. Pandarinathan, and P. Sankar, "A 90μW 15-bit ΔΣ ADC for digital audio," Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Munich, Germany, pp. 198-201, Sept., 2007.
21. R. Naiknaware, and T. Fiez, "142dB ΔΣ ADC with a 100nV LSB in a 3V CMOS process," Proc. of IEEE Custom Integrated Circ. Conf. (CICC), Orlando, USA, pp. 5-8, May, 2000.
22. S. Pavan, and P. Sankar, "A 110μW Single Bit Audio Continuous-time Oversampled Converter with 92.5 dB Dynamic Range," Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Athens, Greece, pp. 320-323, Sept., 2009.
23. H. Park, K. Nam, D. K. Su, K. Vleugels, and B. A. Wooley, "A 0.7-V 100-dB 870-μW Digital Audio ΣΔ Modulator," Symp. VLSI Circ. Digest of Technical Papers, Honolulu, USA, pp. 178-179, June, 2008.
24. J.-Y. Wu, Z. Zhang, R. Subramoniam, and F. Maloberti, "A 107.4 dB SNR multi-bit sigma delta ADC with 1-PPM THD at 0.12 dB from full scale input," IEEE J. Solid-State Circuits, Vol. 44, pp. 3060-3066, Nov., 2009.
25. Y. Chae, I. Lee, and G. Han, "A 0.7V 36μW 85dB-DR audio ΔΣ modulator using class-C inverter," Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, Vol. i, pp. 490-491, Feb., 2008.
26. K. Y. Leung, K. Leung, and D. R. Holberg, "A dual low power 1/2 LSB INL 16b/1Msample/s SAR A/D converter with on-chip microcontroller," Proc. of IEEE Asian Solid-State Circ. Conf. (ASSCC), Hangzhou, China, pp. 51-54, Nov., 2006.