A 107.4 dB SNR multi-bit Sigma Delta ADC with 1-PPM THD at -0.12 dB from full scale input

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 11, 2009, Pages 3060-3066

  Wu, Jian Yi ^a   Zhang, Zhenyong ^a   Subramoniam, Rajaram ^a   Maloberti, Franco ^b  

^a NATIONAL SEMICONDUCTOR CORPORATION   (United States)

^b UNIVERSITY OF PAVIA   (Italy)

Author keywords

DAC with level reduction; Delta sigma ADC; Extended dynamic range; Truncation noise cancellation

Indexed keywords

DAC WITH LEVEL REDUCTION; DELTA SIGMA ADC; DUAL GATE OXIDE; DYNAMIC RANGE; EXTENDED DYNAMIC RANGE; EXTENDED DYNAMICS; FULL SCALE; HIGH-ORDER; INPUT SIGNAL; MULTI-BITS; NOISE-SHAPING; NOVEL TECHNIQUES; POWER CONSUMPTION; QUANTIZERS; SAMPLING FREQUENCIES; SECOND ORDERS; SIGMA DELTA ADC; SIGMA-DELTA MODULATOR; SIGNAL TO NOISE; TRUNCATION NOISE CANCELLATION;

DELTA SIGMA MODULATION; DIGITAL SIGNAL PROCESSORS; MODULATORS; MULTICARRIER MODULATION; SIGNAL TO NOISE RATIO; SPACE DIVISION MULTIPLE ACCESS;

DIGITAL INTEGRATED CIRCUITS;

EID: 70449475589     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2032753     Document Type: Article

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