Thread-level redundancy fault tolerant CMP based on relaxed input replication

Proceedings - 6th International Conference on Computer Sciences and Convergence Information Technology, ICCIT 2011

Volumn , Issue , 2011, Pages 544-549

  Yu, Jiaxin ^a,b   Jian, Dong ^a   Wu, Zhibo ^a   Liu, Hongwei ^a  

^a HARBIN INSTITUTE OF TECHNOLOGY   (China)

^b YANSHAN UNIVERSITY   (China)

Author keywords

CMP; fault tolerance; parallel applications; thread level redundancy

Indexed keywords

CACHE ARCHITECTURE; CHIP MULTIPROCESSORS; CMOS SCALING; CMP; FAULT-TOLERANT; HARDWARE RESOURCES; L2 CACHE; MEMORY OPERATIONS; NON-DETERMINISM; ONE CHIP; PARALLEL APPLICATION; PERFORMANCE LOSS; PROCESS VARIATION; TRANSIENT FAULTS; VOLTAGE FACTORS;

CACHE MEMORY; COMPUTER SCIENCE; FAULT TOLERANCE; INFORMATION TECHNOLOGY; MICROPROCESSOR CHIPS;

REDUNDANCY;

EID: 84869420131     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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