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IEEE International Conference on Computer Design, ICCD 2006

Volumn , Issue , 2006, Pages 120-126

Efficient transient-fault tolerance for multithreaded processors using dual-thread execution

(2) Ma, Yi a Zhou, Huiyang a

a UNIVERSITY OF CENTRAL FLORIDA (United States)

Author keywords

Fault tolerance; Microprocessors; Multi threaded architectures; Redundant systems

Indexed keywords

COMPUTER DESIGNS; COMPUTER SYSTEM DESIGN; CRITICAL RESOURCES; DUAL-CORE EXECUTION; FAULT-TOLERANT; INTERNATIONAL CONFERENCES; MICROPROCESSORS; MULTI-THREADED ARCHITECTURES; MULTI-THREADED PROCESSORS; PERFORMANCE IMPROVEMENTS; PROCESSOR CORES; REDUNDANT SYSTEMS; RESOURCE CONTENTION; SIMULTANEOUS MULTITHREADED ARCHITECTURES; SINGLE CHIPS; SMT ARCHITECTURES; SMT PROCESSORS; TRANSIENT FAULTS; TRANSIENT-FAULT TOLERANCE;

COMPUTER SYSTEMS; ERRORS; FAULT TOLERANCE; FAULT TOLERANT COMPUTER SYSTEMS; RELIABILITY; SPEECH TRANSMISSION; SURFACE MOUNT TECHNOLOGY;

QUALITY ASSURANCE;

EID: 49749109535 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/ICCD.2006.4380804 Document Type: Conference Paper

Times cited : (12)

References (21)

1
- 0033321638
- DIVA: A reliable substrate for deep submicron microarchitecture design
- nd Int. Symp. on Microarch. (MICRO-32), 1999.
- (1999) nd Int. Symp. on Microarch. (MICRO-32)
- Austin, T.¹

2
- 84944390453
- Beating in-order stalls with flea-flicker two pass pipelining
- th Int. Symp. on Microarch. (MICRO-36), 2003.
- (2003) th Int. Symp. on Microarch. (MICRO-36)
- Barnes, R.¹ Nystrom, E.² Sias, J.³ Patel, S.⁴ Navarro, N.⁵ Hwu, W.⁶

3
- 0033719421
- Wattch: A framework for architectural-level power analysis and optimization
- th Int. Symp. on Comp. Arch. (ISCA-27), 2000.
- (2000) th Int. Symp. on Comp. Arch. (ISCA-27)
- Brooks, D.¹ Tiwari, V.² Martonosi, M.³

4
- 0002986475
- The SimpleScalar tool set, v2.0
- June
- D. Burger and T. Austin, "The SimpleScalar tool set, v2.0", Computer Architecture News, vol. 25, June 1997.
- (1997) Computer Architecture News , vol.25
- Burger, D.¹ Austin, T.²

5
- 4143075988
- Improving memory latency aware fetch policies for SMT processors
- th Int. Symp. on High Perf. Computing (ISHPC-5), 2003.
- (2003) th Int. Symp. on High Perf. Computing (ISHPC-5)
- Cazorla, F.¹ Fernandez, E.² Ramirez, A.³ Valero, M.⁴

6
- 0030662863
- Improving data cache performance by pre-executing instructions under a cache miss
- J. Dundas and T. Mudge, "Improving data cache performance by pre-executing instructions under a cache miss", Proc. of the 1997 Int. Conf. on Supercomputing (ICS-97), 1997.
- (1997) Proc. of the 1997 Int. Conf. on Supercomputing (ICS-97)
- Dundas, J.¹ Mudge, T.²

7
- 0038346239
- Transient-fault recovery for chip multiprocessors
- th Int. Symp. on Comp. Arch. (ISCA-30), 2003.
- (2003) th Int. Symp. on Comp. Arch. (ISCA-30)
- Gomma, M.¹ Scarbrough, C.² Vijaykumar, T.³ Pomeranz, I.⁴

8
- 0028736474
- Low power digital design
- M. Horowitz, T. Indermaur, and R. Gonzalez, "Low power digital design", Int. Symp. on Low Power Electronics, 1994.
- (1994) Int. Symp. on Low Power Electronics
- Horowitz, M.¹ Indermaur, T.² Gonzalez, R.³

9
- 33748875821
- Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors
- th Int. Symp. on High Perf. Comp. Arch. (HPCA-12), 2006.
- (2006) th Int. Symp. on High Perf. Comp. Arch. (HPCA-12)
- Kumar, S.¹ Aggarwal, A.²

10
- 84955506994
- Runahead execution: An alternative to very large instruction windows for out-of-order processors
- th Int. Symp. on High Perf. Comp. Arch. (HPCA-9), 2003
- (2003) th Int. Symp. on High Perf. Comp. Arch. (HPCA-9)
- Mutlu, O.¹ Stark, J.² Wilkerson, C.³ Patt, Y.⁴

11
- 0036287327
- Detailed design and evaluation of redundant multithreading alternatives
- th Int. Symp. on Comp. Arch.(ISCA-29), 2002.
- (2002) th Int. Symp. on Comp. Arch.(ISCA-29)
- Mukherjee, S.¹ Kontz, M.² Reinhardt, S.³

12
- 0033726332
- Transient fault detection via simultaneous multithreading
- th Int. Symp. on Comp. Arch. (ISCA-27), 2000.
- (2000) th Int. Symp. on Comp. Arch. (ISCA-27)
- Reinhardt, S.¹ Mukherjee, S.²

13
- 0032597692
- AR-SMT: A microarchitectural approach to fault tolerance in microprocessors
- th Int. Symp. on Fault-Toler. Computing (FTCS-29), 1999.
- (1999) th Int. Symp. on Fault-Toler. Computing (FTCS-29)
- Rotenberg, E.¹

14
- 21644470906
- Efficient Resource Sharing in Concurrent Error Detecting Supersalar Microarchitectures
- th Int. Symp. on Microarch. (MICRO-37), 2004.
- (2004) th Int. Symp. on Microarch. (MICRO-37)
- Smolens, J.¹ Kim, J.² Hoe, J.³ Falsafi, B.⁴

15
- 0034441012
- Slipstream processors: Improving both performance and fault tolerance
- th Int. Conf. on Arch. Support for Prog. Lang, and Operating Sys. (ASPLOS-9), 2000.
- (2000) th Int. Conf. on Arch. Support for Prog. Lang, and Operating Sys. (ASPLOS-9)
- Sundaramoorthy, K.¹ Purser, Z.² Rotenberg, E.³

16
- 0035696665
- Handling long-latency loads in a simultaneous multithreaded processor
- th Int. Symp. on Microarch. (MICRO-34), 2001.
- (2001) th Int. Symp. on Microarch. (MICRO-34)
- Tullsen, D.¹ Brown, J.²

17
- 0029666641
- Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor
- rd Int. Symp. on Comp. Arch. (ISCA-23), 1996.
- (1996) rd Int. Symp. on Comp. Arch. (ISCA-23)
- Tullsen, D.¹ Eggers, S.² Emer, J.³ Levy, H.⁴ Lo, J.⁵ Stamm, R.⁶

18
- 0036290674
- Transient-fault recovery using simultaneous multithreading
- th Int. Symp. on Comp. Arch. (ISCA-29), 2002.
- (2002) th Int. Symp. on Comp. Arch. (ISCA-29)
- Vijaykumar, T.¹ Pomeranz, I.² Cheng, K.³

19
- 49749130305
- Y. Zhang, D. Parikh, K. Sankaranarayanan, K. Skadron, and M. Stan, Hotleakage: a temperature-aware model of sub-threshold and gate leakage for architects, Tech. Reports CS-2003-05, U. Va. Dept. of CS, 2003.
- Y. Zhang, D. Parikh, K. Sankaranarayanan, K. Skadron, and M. Stan, "Hotleakage: a temperature-aware model of sub-threshold and gate leakage for architects", Tech. Reports CS-2003-05, U. Va. Dept. of CS, 2003.

20
- 33644919336
- Dual-core execution: Building a highly scalable single-thread instruction window
- H. Zhou, "Dual-core execution: building a highly scalable single-thread instruction window", Proc. of the 2005 Int. Conf. on Para. Arch. And Compiler Tech, (PACTOS), 2005.
- (2005) Proc. of the 2005 Int. Conf. on Para. Arch. And Compiler Tech, (PACTOS)
- Zhou, H.¹

21
- 49749105858
- A case for fault-tolerance and performance enhancement using Chip Multiprocessors
- Arch. Letters. September
- H. Zhou, "A case for fault-tolerance and performance enhancement using Chip Multiprocessors", IEEE Comp. Arch. Letters. September 2005.
- (2005) IEEE Comp
- Zhou, H.¹

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