A single-channel, 1.25-GS/s, 6-bit, 6.08-mW asynchronous successive-approximation ADC with improved feedback delay in 40-nm CMOS

IEEE Journal of Solid-State Circuits

Volumn 47, Issue 10, 2012, Pages 2444-2453

  Jiang, Tao ^a   Liu, Wing ^b   Zhong, Freeman Y ^c   Zhong, Charlie ^d   Hu, Kangmin ^e   Chiang, Patrick Yin ^a  

^a Oregon State University   (United States)

^b ALTERA CORPORATION   (United States)

^c AGERE SYSTEMS   (United States)

^d NVIDIA   (United States)

^e BROADCOM CORPORATION   (United States)

Author keywords

Analog to digital converter (ADC); asynchronous logic; binary successive approximation (SA) algorithm; single channel ADC

Indexed keywords

ANALOG TO DIGITAL CONVERTERS; ASYNCHRONOUS LOGIC; CORE AREA; DIGITAL FEEDBACK; DIGITAL LOGIC; FEEDBACK DELAY; MEASUREMENT RESULTS; QUANTIZERS; SAMPLING RATES; SINGLE-CHANNEL; SUCCESSIVE-APPROXIMATION ADC;

CLOCKS; DIGITAL INTEGRATED CIRCUITS;

APPROXIMATION ALGORITHMS;

EID: 84867401299     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2012.2204543     Document Type: Article

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