A 3.5 GS/s 5-b flash ADC in 90 nm CMOS

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2006, Pages 489-492

  Park, Sunghyun ^a,b   Palaskas, Yorgos ^b   Ravi, Ashoke ^b   Bishop, Ralph E ^b   Flynn, Michael P ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; ELECTRIC POTENTIAL; SWITCHED FILTERS;

CLOCK BUFFER; OFFSET CANCELLATION;

CMOS INTEGRATED CIRCUITS;

EID: 39049083870     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2006.320890     Document Type: Conference Paper

References (5)

1. K. Poulton, et al., "A 20 GS/s 8 b ADC with a 1 MB memory in 0.18μm CMOS," International Solid-State Circuits Conference, Feb. 2003.
2. A. Varzaghani and C.-K. K. Yang, "A 6GS/s 4-bit receiver analog-to-digital converter with embedded DFT," Symposium on VLSI Circuits, Jun. 2005.
3. S. Park, Y. Palaskas, and M. P. Flynn, "A 4GS/s 4b flash ADC in 0.18μm CMOS," International Solid-State Circuits Conference, Feb. 2006.
4. S. Park and M. P. Flynn, "Design techniques for high performance CMOS flash analog-to-digital converters," European Conference on Circuit Theory and Design, Aug. 2005.
5. M. Choi and A. A. Abidi, "A 6-b 1.3-Gsample/s A/D converter in 0.35μm CMOS," IEEE J. Solid-State Circuits, vol. 36, pp. 1847-1858, Dec. 2001.