A 1 GS/s 6 bit 6.7 mW successive approximation ADC using asynchronous processing

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 8, 2010, Pages 1469-1478

  Yang, Jing ^a   Naing, Thura Lin ^a   Brodersen, Robert W ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Analog to digital conversion; asynchronous logic circuits; binary successive approximation algorithm; cognitive radios; metastability; semi closed loop; series capacitor array; time interleaving

Indexed keywords

ASYNCHRONOUS LOGIC CIRCUITS; CLOSED LOOPS; COGNITIVE RADIO; METASTABILITIES; SERIES CAPACITORS; SUCCESSIVE APPROXIMATIONS; TIME-INTERLEAVING;

ANALOG CIRCUITS; APPROXIMATION THEORY; CAPACITANCE; CAPACITORS; DIGITAL CIRCUITS; LOGIC CIRCUITS; RADIO; SWITCHING CIRCUITS; TIME VARYING SYSTEMS;

APPROXIMATION ALGORITHMS;

EID: 77955133266     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2048139     Document Type: Conference Paper

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