Single-channel, 1.25-GS/s, 6-bit, loop-unrolled asynchronous SAR-ADC in 40nm-CMOS

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2010, Pages

  Jiang, Tao ^a   Liu, Wing ^b   Zhong, Freeman Y ^b   Zhong, Charlie ^b   Chiang, Patrick Y ^a  

^a OREGON STATE UNIVERSITY   (United States)

^b AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CORE AREA; DIGITAL FEEDBACK; SAMPLE RATE; SINGLE CHANNELS; SINGLE-CHANNEL; SUCCESSIVE APPROXIMATIONS;

APPROXIMATION THEORY; COMPARATORS (OPTICAL); INTEGRATED CIRCUITS;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 78649810900     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2010.5617411     Document Type: Conference Paper

References (7)

1. S.-W. M. Chen and R. W. Brodersen, "A 6-bit 600-MS/s 5.3mW asynchronous ADC in 0.13-μm CMOS," IEEE JSSC, vol. 41, no. 12, pp. 2669-2680, Dec 2006.
2. Z. Cao, S. Yan and Y. Li, "A 32mW 1.25GS/s 6b 2b/step SAR ADC in 0.13μm CMOS," IEEE JSSC, vol. 44, no. 3, pp. 862-873, Mar 2009.
3. Y.-Z. Liu, S.-J. Chang, Y.-T. Liu, C.-C Liu and G.-Y. Huang, "A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS," ISSCC Dig. of Tech. Papers, pp. 80-81, Feb 2009.
4. J. Yang, T. L. Naing and B. Brodersen, "A 1-GS/s 6-bit 6.7-mW ADC in 65nm CMOS," CICC 2009, pp. 287-290.
5. Y. M. Greshishchev, et. al., "A 40GS/s 6b ADC in 65nm CMOS", ISSCC Dig. of Tech. Papers, pp. 390-391, Feb 2010.
6. C.-C. Liu, et. al., "A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation," ISSCC Dig. of Tech. Papers, pp. 386-387, Feb 2010.
7. M. Dessouky and A. Kaiser, "Very low-voltage digital-audio ΔΣ modulator with 88-dB dynamic range using local switch bootstrapping," IEEE JSSC, vol. 36, no. 3, pp. 349-355, Mar. 2001.