A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with tri-level comparator in 40nm CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2011, Pages 262-263

  Shikata, Akira ^a   Sekimoto, Ryota ^a   Kuroda, Tadahiro ^a   Ishikuro, Hiroki ^a  

^a KEIO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERTERS; CALIBRATION PROCEDURE; CAPACITOR ARRAYS; CAPACITOR MISMATCH; CMOS PROCESSS; DIGITAL-TO-ANALOG CONVERTERS; LOW VOLTAGE OPERATION; POWER EFFICIENT; POWER SUPPLY; RE-CONFIGURABLE; SPEED REQUIREMENT; SUCCESSIVE APPROXIMATION REGISTER; UNIT CAPACITANCE;

CAPACITORS; CMOS INTEGRATED CIRCUITS; COMPARATORS (OPTICAL); DIGITAL INTEGRATED CIRCUITS; VLSI CIRCUITS;

ANALOG TO DIGITAL CONVERSION;

EID: 80052678511     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. M. V. Elzakker, et al., "A 10-bit Charge-Redistribution ADC Consuming 1.9μW at 1MS/s," IEEE Journal of Solid-State Circuits, Vol.45, No.5, May 2010 pp.1007-1015
2. Chun-Cheng Liu, et al., "A 1V 11fJ/Conversion-Step 10bit 10MS/s Asynchronous SAR ADC in 0.18mm CMOS," IEEE Symposium on VLSI Circuits, Jun, 2010, pp. 241-242.
3. Joshua J. Kang and Michael P. Flynn, "A 12b 11MS/s Successive Approximation ADC with two comparators in 0.13mm CMOS,"IEEE Symposium on VLSI Circuits, pp.240-241, June, 2009.
4. Pieter Harpe, et al., "A 30fJ/Conversion-Step 8b 0-to-10MS/s Asynchronous SAR ADC in 90nm CMOS," IEEE, ISSCC 2010, pp.388-389
5. Seon-Kyoo Lee, et al., "A 1.3μW 0.6V 8.7-ENOB Successive Approximation ADC in a 0.18mm CMOS," IEEE Symposium on VLSI Circuits, pp.242-243, June, 2009.