-
2
-
-
34748822876
-
Specification, synthesis, and simulation of transactor processes
-
DOI 10.1109/TCAD.2007.895792
-
F. Balarin and R. Passerone, "Specification, Synthesis, and Simulation of Transactor Processes," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 10, pp. 1749-1762, Oct. 2007. (Pubitemid 47483017)
-
(2007)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.26
, Issue.10
, pp. 1749-1762
-
-
Balarin, F.1
Passerone, R.2
-
3
-
-
49749128752
-
Integrating RTL IPs into TLM designs through automatic transactor generation
-
N. Bombieri, N. Deganello, and F. Fummi, "Integrating RTL IPs into TLM Designs through Automatic Transactor Generation," Proc. Conf. Design, Automation and Test in Europe (DATE), pp. 15-20, 2008.
-
(2008)
Proc. Conf. Design, Automation and Test in Europe (DATE)
, pp. 15-20
-
-
Bombieri, N.1
Deganello, N.2
Fummi, F.3
-
4
-
-
33745183745
-
Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths
-
DOI 10.1145/1109118.1109121
-
M. Fujita, "Equivalence Checking between Behavioral and RTL Descriptions with Virtual Controllers and Datapaths," ACM Trans. Design Automation of Electronic Systems , vol. 10, no. 4, pp. 610-626, 2005. (Pubitemid 43909215)
-
(2005)
ACM Transactions on Design Automation of Electronic Systems
, vol.10
, Issue.4
, pp. 610-626
-
-
Fujita, M.1
-
5
-
-
22944455550
-
System level validation using formal techniques
-
DOI 10.1049/ip-cdt:20045073, Embedded Microelectronic Systems: Status and Trends (Part 2)
-
R. Drechsler and D. Grosse, "System Level Validation Using Formal Techniques," IEE Proc.-Computer and Digital Techniques, vol. 152, no. 3, pp. 393-406, 2005. (Pubitemid 41048276)
-
(2005)
IEE Proceedings: Computers and Digital Techniques
, vol.152
, Issue.3
, pp. 393-406
-
-
Drechsler, R.1
Grosse, D.2
-
6
-
-
27644588866
-
An industrially effective environment for formal hardware verification
-
Sept
-
C.-J. Seger, R. Jones, J. O'Leary, T. Melham, M. Aagaard, C. Barrett, and D. Syme, "An Industrially Effective Environment for Formal Hardware Verification," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 9, pp. 1381-1405, Sept. 2005.
-
(2005)
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems
, vol.24
, Issue.9
, pp. 1381-1405
-
-
Seger, C.-J.1
Jones, R.2
O'Leary, J.3
Melham, T.4
Aagaard, M.5
Barrett, C.6
Syme, D.7
-
8
-
-
57849147619
-
Scalable and scalably-verifiable sequential synthesis
-
A. Mishchenko, M. Case, R. Brayton, and S. Jang, "Scalable and Scalably-Verifiable Sequential Synthesis," Proc. ACM/IEEE Int'l Conf. Computer-Aided Design (ICCAD), pp. 234-241, 2008.
-
(2008)
Proc. ACM/IEEE Int'l Conf. Computer-Aided Design (ICCAD)
, pp. 234-241
-
-
Mishchenko, A.1
Case, M.2
Brayton, R.3
Jang, S.4
-
9
-
-
84879488694
-
Combinational techniques for sequential equivalence checking
-
H. Savoj, D. Berthelot, A. Mishchenko, and R. Brayton, "Combinational Techniques for Sequential Equivalence Checking," Proc. 19th ACM/IEEE Int'l Workshop Logic and Synthesis (IWLS), 2010.
-
(2010)
Proc. 19th ACM/IEEE Int'l Workshop Logic and Synthesis (IWLS)
-
-
Savoj, H.1
Berthelot, D.2
Mishchenko, A.3
Brayton, R.4
-
10
-
-
0036056415
-
A practical and efficient method for compare-point matching
-
D. Anastasakis, R. Damiano, H.-K. Mah, and T. Stanion, "A Practical and Efficient Method for Compare-Point Matching," Proc. 39th ACM/IEEE Ann. Design Automation Conf. (DAC), pp. 305-310, 2002.
-
(2002)
Proc. 39th ACM/IEEE Ann. Design Automation Conf. (DAC)
, pp. 305-310
-
-
Anastasakis, D.1
Damiano, R.2
Mah, H.-K.3
Stanion, T.4
-
12
-
-
34548835962
-
Automatic decomposition for sequential equivalence checking of system level and RTL descriptions
-
1695903, Proceedings - Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, MEMOCODE'06
-
S. Vasudevan, V. Viswanath, J. Abraham, and J. Tu, "Automatic Decomposition for Sequential Equivalence Checking of System Level and RTL Descriptions," Proc. Fourth ACM and IEEE Int'l Conf. Formal Methods and Models Co-Design (MEMOCODE), pp. 71-80, 2006. (Pubitemid 351410293)
-
(2006)
Proceedings - Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, MEMOCODE'06
, pp. 71-80
-
-
Vasudevan, S.1
Viswanath, V.2
Abraham, J.A.3
Tu, J.4
-
13
-
-
16244422642
-
Checking consistency of C and Verilog using predicate abstraction and induction
-
1C.4, ICCAD-2004 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
-
D. Kroening and E. Clarke, "Checking Consistency of C and Verilog Using Predicate Abstraction and Induction," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD), pp. 66-72, 2004. (Pubitemid 40449215)
-
(2004)
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
, pp. 66-72
-
-
Kroening, D.1
Clarke, E.2
-
14
-
-
33751397158
-
Embedded tutorial: Formal equivalence checking between system-level models and RTL
-
A. Koelbl, Y. Lu, and A. Mathur, "Embedded Tutorial: Formal Equivalence Checking between System-Level Models and RTL," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD), pp. 965-971, 2005.
-
(2005)
Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD)
, pp. 965-971
-
-
Koelbl, A.1
Lu, Y.2
Mathur, A.3
-
15
-
-
70350712435
-
Non-cycle-accurate sequential equivalence checking
-
P. Chauhan, D. Goyal, G. Hasteer, A. Mathur, and N. Sharma, "Non-Cycle-Accurate Sequential Equivalence Checking," Proc. 46th ACM/IEEE Design Automation Conf. (DAC), pp. 460-465, 2009.
-
(2009)
Proc. 46th ACM/IEEE Design Automation Conf. (DAC)
, pp. 460-465
-
-
Chauhan, P.1
Goyal, D.2
Hasteer, G.3
Mathur, A.4
Sharma, N.5
-
16
-
-
34548837204
-
Towards equivalence checking between TLM and RTL models
-
DOI 10.1109/MEMCOD.2007.371236, 4231785, Proceedings - Fifth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, MEMOCODE'07
-
N. Bombieri, F. Fummi, G. Pravadelli, and J. Marques-Silva, "Towards Equivalence Checking between TLM and RTL Models," Proc. Fifth IEEE/ACM Int'l Conf. Formal Methods and Models for Codesign (MEMOCODE), pp. 113-122, 2007. (Pubitemid 47439947)
-
(2007)
Proceedings - Fifth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, MEMOCODE'07
, pp. 113-122
-
-
Bombieri, N.1
Fummi, F.2
Pravadelli, G.3
Marques-Silva, J.4
-
17
-
-
84886742515
-
EFSM manipulation to increase high-level ATPG efficiency
-
G. Di. Guglielmo, F. Fummi, C. Marconcini, and G. Pravadelli, "EFSM Manipulation to Increase High-Level ATPG Efficiency," Proc. Seventh Int'l Symp. Quality Electronic Design (ISQED), 2006.
-
(2006)
Proc. Seventh Int'l Symp. Quality Electronic Design (ISQED)
-
-
Di. Guglielmo, G.1
Fummi, F.2
Marconcini, C.3
Pravadelli, G.4
-
18
-
-
4243696949
-
-
Technical Report ICS-97-26, Univ. of California, Irvine
-
D. Gajski, J. Zhu, and R. Domer, "Essential Issue in Codesign," Technical Report ICS-97-26, Univ. of California, Irvine, 1997.
-
(1997)
Essential Issue in Codesign
-
-
Gajski, D.1
Zhu, J.2
Domer, R.3
-
19
-
-
0002063138
-
Automatic generation of functionial vectors using the extended finite state machine model
-
K.-T. Cheng and A.S. Krishnakumar, "Automatic Generation of Functional Vectors Using the Extended Finite State Machine Model," ACM Trans. Design Automation of Electronic Systems, vol. 1, no. 1, pp. 57-79, 1996. (Pubitemid 126767530)
-
(1996)
ACM Transactions on Design Automation of Electronic Systems
, vol.1
, Issue.1
, pp. 57-79
-
-
Cheng, K.-T.1
Krishnakumar, A.S.2
-
20
-
-
84879493909
-
-
OSCI
-
OSCI, http://www.systemc.org, 2009.
-
(2009)
-
-
-
22
-
-
34548813299
-
Execution semantics and formalisms for multi-abstraction tlm assertions
-
W. Ecker, V. Esen, and M. Hull, "Execution Semantics and Formalisms for Multi-Abstraction TLM Assertions," Proc. Fourth ACM and IEEE Int'l Conf. on Formal Methods and Models for Co-Design (MEMOCODE), pp. 93-79, 2006.
-
(2006)
Proc. Fourth ACM and IEEE Int'l Conf. on Formal Methods and Models for Co-Design (MEMOCODE)
, pp. 93-79
-
-
Ecker, W.1
Esen, V.2
Hull, M.3
-
23
-
-
0017996760
-
Time, clocks, and the ordering of events in a distributed system
-
DOI 10.1145/359545.359563
-
L. Lamport, "Time, Clocks, and the Ordering of Events in a Distributed System," Comm. ACM, vol. 21, no. 7, pp. 558-565, 1978. (Pubitemid 8615486)
-
(1978)
Communications of the ACM
, vol.21
, Issue.7
, pp. 558-565
-
-
Lamport Leslie1
-
24
-
-
84879476464
-
-
ESD Group Univ. of Verona EDALab s.r.l
-
ESD Group, Univ. of Verona, EDALab s.r.l. "A2T." http://hifsuite.edalab.it, 2010.
-
(2010)
A2T
-
-
-
25
-
-
33646941895
-
An integrated design and verification methodology for reconfigurable multimedia systems
-
DOI 10.1109/DATE.2005.61, 1395832, Proceedings - Design, Automation and Test in Europe - Designers' Forum, DATE '05
-
M. Borgatti, A. Capello, U. Rossi, J.-L. Lambert, I. Moussa, F. Fummi, and G. Pravadelli, "An Integrated Design and Verification Methodology for Reconfigurable Multimedia System," Proc. Conf. Design, Automation and Test in Europe (DATE), pp. 266-271, 2005. (Pubitemid 44172244)
-
(2005)
Proceedings -Design, Automation and Test in Europe, DATE '05
, vol.2005
, pp. 266-271
-
-
Borgatti, M.1
Capello, A.2
Rossi, U.3
Lambert, J.-L.4
Moussa, I.5
Fummi, F.6
Pravadelli, G.7
-
26
-
-
70449461110
-
-
Politecnico di Torino
-
Politecnico di Torino "ITC-99 Benchmarks," http://www.cad. polito.it/tools/itc99.html, 1999.
-
(1999)
ITC-99 Benchmarks
-
-
-
27
-
-
84879464842
-
-
Coconut Project: Final Report, http://www.coconut-project.eu/files/FP7- 2007-IST-1-217069-Coconut-D7.1.pdf, 2010.
-
(2010)
Coconut Project: Final Report
-
-
|