-
2
-
-
0043035023
-
The Transaction-Based Verification Methodology
-
Tech. Rep. CDNL-TR-2000-0825, Cadence Berkeley Labs, 2000
-
D. Brahme, S. Cox, J. Gallo, M. Glasser, W. Grundmann, C. N. Ip, W. Paulsen, J. Pierce, J. Rose, D. Shea, and K. Whiting. The Transaction-Based Verification Methodology. Tech. Rep. CDNL-TR-2000-0825, Cadence Berkeley Labs, 2000.
-
-
-
Brahme, D.1
Cox, S.2
Gallo, J.3
Glasser, M.4
Grundmann, W.5
Ip, C.N.6
Paulsen, W.7
Pierce, J.8
Rose, J.9
Shea, D.10
Whiting, K.11
-
4
-
-
34547757490
-
On PSL Properties Re-use in SoC Design Flow based on Transaction Level Modeling
-
N. Bombieri, A. Fedeli, and F. Fummi. On PSL Properties Re-use in SoC Design Flow based on Transaction Level Modeling. In Proc. of IEEE MTV, pp. 127-132. 2005.
-
(2005)
Proc. of IEEE MTV
, pp. 127-132
-
-
Bombieri, N.1
Fedeli, A.2
Fummi, F.3
-
5
-
-
34548354658
-
Incremental ABV for Functional Validation of TL-to-RTL Design Refinement
-
N. Bombieri, F. Fummi, and G. Pravadelli. Incremental ABV for Functional Validation of TL-to-RTL Design Refinement. In Proc. of ACM/IEEE DATE. 2007.
-
(2007)
Proc. of ACM/IEEE DATE
-
-
Bombieri, N.1
Fummi, F.2
Pravadelli, G.3
-
6
-
-
33745183745
-
Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths
-
M. Fujita. Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths. ACM Trans. Des. Autom. Electron. Syst., vol. 10(4):pp. 610-626, 2005.
-
(2005)
ACM Trans. Des. Autom. Electron. Syst
, vol.10
, Issue.4
, pp. 610-626
-
-
Fujita, M.1
-
9
-
-
0032314158
-
Robust latch mapping for combinational equivalence checking
-
J. R. Burch and V. Singhal. Robust latch mapping for combinational equivalence checking. In Proc. of IEEE ICCAD, pp. 563-569. 1998.
-
(1998)
Proc. of IEEE ICCAD
, pp. 563-569
-
-
Burch, J.R.1
Singhal, V.2
-
10
-
-
33751397158
-
Embedded tutorial: Formal equivalence checking between system-level models and RTL
-
A. Koelbl, Y. Lu, and A. Mathur. Embedded tutorial: formal equivalence checking between system-level models and RTL. In Proc. of ACM/IEEE ICCAD, pp. 965-971. 2005.
-
(2005)
Proc. of ACM/IEEE ICCAD
, pp. 965-971
-
-
Koelbl, A.1
Lu, Y.2
Mathur, A.3
-
11
-
-
34548835962
-
Automatic decomposition for sequential equivalence checking of system level and RTL descriptions
-
S. Vasudevan, V. Viswanath, J. Abraham, and J. Tu. Automatic decomposition for sequential equivalence checking of system level and RTL descriptions. In Proc. of ACM/IEEE MEMOCODE, pp. 71-80. 2006.
-
(2006)
Proc. of ACM/IEEE MEMOCODE
, pp. 71-80
-
-
Vasudevan, S.1
Viswanath, V.2
Abraham, J.3
Tu, J.4
-
12
-
-
16244422642
-
Checking consistency of C and Verilog using predicate abstraction and induction
-
D. Kroening and E. Clarke. Checking consistency of C and Verilog using predicate abstraction and induction. In Proc. of ACM/IEEE ICCAD, pp. 66-72. 2004.
-
(2004)
Proc. of ACM/IEEE ICCAD
, pp. 66-72
-
-
Kroening, D.1
Clarke, E.2
-
13
-
-
34548813299
-
Execution semantics and formalisms for multi-abstraction TLM assertions
-
W. Ecker, V. Esen, and M. Hull. Execution semantics and formalisms for multi-abstraction TLM assertions. In Proc. of ACM/IEEE MEMOCODE, pp. 93-79. 2006.
-
(2006)
Proc. of ACM/IEEE MEMOCODE
, pp. 93-79
-
-
Ecker, W.1
Esen, V.2
Hull, M.3
-
14
-
-
0017996760
-
Time, clocks, and the ordering of events in a distributed system
-
L. Lamport. Time, clocks, and the ordering of events in a distributed system. Communications of the ACM, vol. 21(7):pp. 558-565, 1978.
-
(1978)
Communications of the ACM
, vol.21
, Issue.7
, pp. 558-565
-
-
Lamport, L.1
-
16
-
-
34548819828
-
-
Open Core Protocol International Partnership OCP-IP
-
Open Core Protocol International Partnership (OCP-IP). http://www.ocpip.org.
-
-
-
-
18
-
-
4243696949
-
Essential Issue in Codesign
-
Technical report ICS-97-26, University of California, Irvine
-
D. Gajski, J. Zhu, and R. Domer. Essential Issue in Codesign. Technical report ICS-97-26, University of California, Irvine, 1997.
-
(1997)
-
-
Gajski, D.1
Zhu, J.2
Domer, R.3
-
19
-
-
0002063138
-
Automatic Generation of Functional Vectors Using the Extended Finite State Machine Model
-
K. Cheng and A. Krishnakumar. Automatic Generation of Functional Vectors Using the Extended Finite State Machine Model. ACM Trans. on Design Automation of Electronic Systems, vol. 1(1):pp. 57-79, 1996.
-
(1996)
ACM Trans. on Design Automation of Electronic Systems
, vol.1
, Issue.1
, pp. 57-79
-
-
Cheng, K.1
Krishnakumar, A.2
-
20
-
-
33646941895
-
An Integrated Design and Verification Methodology for Reconfigurable Multimedia System
-
M. Borgatti, A. Capello, F. Fummi, J.-L. Lambert, I. Moussa, G. Pravadelli, and U. Rossi. An Integrated Design and Verification Methodology for Reconfigurable Multimedia System. In IEEE DATE, pp. 266-271. 2005.
-
(2005)
IEEE DATE
, pp. 266-271
-
-
Borgatti, M.1
Capello, A.2
Fummi, F.3
Lambert, J.-L.4
Moussa, I.5
Pravadelli, G.6
Rossi, U.7
|