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Volumn , Issue , 2007, Pages 113-122

Towards equivalence checking between TLM and RTL models

Author keywords

[No Author keywords available]

Indexed keywords

ABSTRACTING; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; REQUIREMENTS ENGINEERING;

EID: 34548837204     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MEMCOD.2007.371236     Document Type: Conference Paper
Times cited : (34)

References (21)
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  • 4
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  • 5
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    • Incremental ABV for Functional Validation of TL-to-RTL Design Refinement
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    • Bombieri, N.1    Fummi, F.2    Pravadelli, G.3
  • 6
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    • Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths
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    • Fujita, M.1
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  • 10
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    • Embedded tutorial: Formal equivalence checking between system-level models and RTL
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    • (2005) Proc. of ACM/IEEE ICCAD , pp. 965-971
    • Koelbl, A.1    Lu, Y.2    Mathur, A.3
  • 11
    • 34548835962 scopus 로고    scopus 로고
    • Automatic decomposition for sequential equivalence checking of system level and RTL descriptions
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.