Scalable and scalably-verifiable sequential synthesis

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2008, Pages 234-241

  Mishchenko, Alan ^a   Case, Michael ^a   Brayton, Robert ^a   Stephen, Jang ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b XILINX INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AND VERIFICATIONS; EFFICIENT IMPLEMENTATIONS; INDUSTRIAL BENCHMARKS; SCAN CHAINS; SEQUENTIAL SYNTHESIS; TEST VECTORS;

COMPUTER AIDED DESIGN;

EID: 57849147619     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2008.4681580     Document Type: Conference Paper

References (27)

1. J. Baumgartner and A. Kuehlmann, "Min-area retiming on flexible circuit structures", Proc. ICCAD '01, pp. 176-182
2. J. Baumgartner, H. Mony, V. Paruthi, R. Kanzelman, and G. Janssen, "Scalable sequential equivalence checking across arbitrary design transformations". Proc. ICCD '06.
3. Berkeley Logic Synthesis and Verification Group. ABC: A System for Sequential Synthesis and Verification. Release 70930. http://www-cad.eecs. berkeley.edu/~alanmi/abc
4. A. Biere, A. Cimatti, E. M. Clarke, and Y. Zhu, "Symbolic model checking without BDDs". Proc. TACAS '99, pp. 193-207.
5. P. Bjesse and K. Claessen. "SAT-based verification without state space traversal". Proc. FMCAD'00. LNCS, Vol. 1954, pp. 372-389.
6. P. Bjesse and J. Kukula, "Automatic generalized phase abstraction for formal verification", Proc. ICCAD'06, pp. 1076-1082.
7. S. Chatterjee, A. Mishchenko, R. Brayton, X. Wang, and T. Kam, "Reducing structural bias in technology mapping", Proc. ICCAD '05, pp. 519-526.
8. J. Cong and Y. Ding, "FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs", IEEE Trans. CAD, vol. 13(1), January 1994, pp. 1-12.
9. N. Een and N. Sörensson, "An extensible SAT-solver". SAT '03. http://www.cs.chalmers.se/Cs/Research/FormalMethods/MiniSat
10. C. A. J. van Eijk. Sequential equivalence checking based on structural similarities, IEEE TCAD, 19(7), July 2000, pp. 814-819.
11. IWLS 2005 Benchmarks. http://iwls.org/iwls2005/benchmarks.html
12. J.-H. Jiang and R.Brayton, "Retiming and resynthesis: A complexity perspective". IEEE TCAD, Vol. 25 (12), Dec. 2006, pp. 2674-2686.
13. J.-H. Jiang and W.-L. Hung, "Inductive equivalence checking under retiming and resynthesis", Proc. ICCAD '07, pp. 326-333
14. A. Kuehlmann, "Dynamic transition relation simplification for bounded property checking". Proc. ICCAD '04, pp. 50-57.
15. B. Lin and A. R. Newton, "Exact removal of redundant state registers using Binary Decision Diagrams," Proc. IFIP TC 10/WG 10.5 Intl Conf. VLSI '91, Edinburgh, Scotland, pp. 277-286.
16. F. Lu, L. Wang, K. Cheng, J. Moondanos, and Z. Hanna, "A signal correlation guided ATPG solver and its applications for solving difficult industrial cases," Proc. DAC '03, pp. 668-673.
17. F. Lu and T. Cheng. "IChecker: An efficient checker for inductive invariants". Proc. HLDVT '06, pp. 176-180.
18. K. L. McMillan. "Interpolation and SAT-Based model checking". Proc. CAV'03, pp.1-33
19. A. Mishchenko, S. Chatterjee, R. Jiang, and R. Brayton, "FRAIGs: A unifying representation for logic synthesis and verification", ERL Technical Report, EECS Dept., U. C. Berkeley, March 2005.
20. A. Mishchenko, S. Chatterjee, R. Brayton, and N. Een, "Improvements to combinational equivalence checking", Proc. ICCAD'06, pp. 836-843
21. A. Mishchenko, S. Cho, S. Chatterjee, and R. Brayton, "Combinational and sequential mapping with priority cuts", Proc. ICCAD '07.
22. A. Mishchenko, S. Chatterjee, and R. Brayton, "DAG-aware AIG rewriting: A fresh look at combinational logic synthesis", Proc. DAC '06, pp. 532-536.
23. H. Mony, J. Baumgartner, V. Paruthi, and R. Kanzelman. "Exploiting suspected redundancy without proving it". Proc. DAC'05.
24. P. Pan and C.-C. Lin, "A new retiming-based technology mapping algorithm for LUT-based FPGAs," Proc. FPGA '98, pp. 35-42.
25. E. Sentovich et al. "SIS: A system for sequential circuit synthesis". Tech. Rep. UCB/ERI, M92/41, ERL, Dept. of EECS, UC Berkeley, 1992.
26. E. M. Sentovich, H. Toma, and G. Berry, "Efficient latch optimization using exclusive sets", Proc. DAC'97, pp. 8-11.
27. http://www.eecs.berkel.ey.edu/~alanmi/publications/other/vss.pdf