Automatic decomposition for sequential equivalence checking of system level and RTL descriptions

Proceedings - Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, MEMOCODE'06

Volumn , Issue , 2006, Pages 71-80

  Vasudevan, Shobha ^a   Viswanath, Vinod ^b   Abraham, Jacob A ^a   Tu, Jiajin ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC DECOMPOSITION; REGISTER TRANSFER LEVEL (RTL); SEQUENTIAL EQUIVALENCE CHECKING; SYMBOLIC EXPRESSIONS;

COMPUTATIONAL COMPLEXITY; COMPUTER PROGRAMMING LANGUAGES; DECODING; MICROPROCESSOR CHIPS; PROBLEM SOLVING; VITERBI ALGORITHM;

SYSTEMS ANALYSIS;

EID: 34548835962     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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