Specification, synthesis, and simulation of transactor processes

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 26, Issue 10, 2007, Pages 1749-1762

  Balarin, Felice ^a,b   Passerone, Roberto ^a,c  

^a IEEE

^b CADENCE DESIGN SYSTEMS   (United States)

^c UNIVERSITY OF TRENTO   (Italy)

Author keywords

Code generation; Finite state machine (FSM) simulation; Property specification language (PSL); Standard co emulation modeling interface (SCE MI); State explosion; SystemC; Transaction level models (TLMs); Transactor; Verification; Verilog

Indexed keywords

ALGORITHMS; AUTOMATIC PROGRAMMING; COMPUTER PROGRAMMING LANGUAGES; COMPUTER SIMULATION; FINITE AUTOMATA; INTERFACES (COMPUTER);

FUNCTION-CALL-BASED COMMUNICATION; REGISTER-TRANSFER-LEVEL (RTL) BLOCKS; SIGNAL-BASED COMMUNICATION; STANDARD CO-EMULATION MODELING INTERFACE (SCE-MI); STATE-EXPLOSION PROBLEMS; TRANSACTION-LEVEL MODELS; TRANSACTOR PROCESSES; VERILOG;

DESIGN AIDS;

EID: 34748822876     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2007.895792     Document Type: Article

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