Embedded tutorial: Formal equivalence checking between system-level models and RTL

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2005, Issue , 2005, Pages 965-971

  Koelbl, Alfred ^a   Yuan, Lu ^b   Mathur, Anmol ^c  

^a SYNOPSYS INC   (United States)

^b Broadcom ^*

^c Calypto Design Systems   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 33751397158     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2005.1560201     Document Type: Conference Paper

References (9)

1. Alfred Koelbl, James Kukula, and Robert Damiano, Symbolic RTL simulation. In Proceedings of DAC 2001.
2. Daniel Kroening, Edmund Clarke, and Karen Yorav, Behavioral consistency of C and Verilog programs using bounded model checking. In Proceedings of DAC 2003, pages 368-371. ACM Press, 2003.
3. Daniel Kroening and Natasha Sharygina, Formal Verification of Systeme by Automatic Hardware/Software Partitioning. In Proceedings of Memocode 2005.
4. Daniel Kroening and Edmund Clarke, Checking Consistency of C and Verilog using Predicate Abstraction and Induction. In Proceedings of ICCAD 2004.
5. http://www.systemc.org.
6. Luc Semeria, Andrew Seawright, Renu Mehra, Daniel Ng, Arjuna Ekanayake, and Barry Pangrle. RTL C-based methodology for designing and verifying a multi-threaded processor. In Proc. of the 39th DAC, pages 123-128. ACM Press, 2002.
7. Carl Pixley, "A theory and implementation of sequential hardware equivalence," IEEE Trans. Computer-Aided Design, pp. 1,469-1,478, Dec. 1992.
8. Matthew W. Moskewicz, Conor F. Madigan, Ying Zhao, Lintao Zhang, and Sharad Malik. Chaff: Engineering an efficient SAT solver. In Proceedings of the 38th Design Automation Conference (DAC'01), pages 530-535, June 2001.
9. Madhu K. Iyer, G. Parthasarathy, and K.-T Cheng, SATORI - A Fast Sequential SAT solver for Circuits, In Proc. of ICCAD, pages 123-128. 2003.