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Volumn , Issue , 2009, Pages 460-465

Non-cycle-accurate sequential equivalence checking

Author keywords

Formal verification; High level synthesis; Model checking; Sequential equivalence checking; Unit product machine

Indexed keywords

EQUIVALENCE CLASSES; FORMAL VERIFICATION; HIGH LEVEL SYNTHESIS;

EID: 70350712435     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1629911.1630033     Document Type: Conference Paper
Times cited : (25)

References (21)
  • 1
    • 84947229460 scopus 로고    scopus 로고
    • A framework for microprocessor correctness statements
    • M. Aagaard, B. Cook, N. A. Day, and R. B. Jones. A framework for microprocessor correctness statements. In CHARME, pp. 433-448, 2001.
    • (2001) CHARME , pp. 433-448
    • Aagaard, M.1    Cook, B.2    Day, N.A.3    Jones, R.B.4
  • 2
    • 49749112061 scopus 로고    scopus 로고
    • Scalable sequential equivalence checking across arbitrary design transformations
    • J. Baumgartner, H. Mony, V. Paruthi, R. Kanzelman, and G. Janssen. Scalable sequential equivalence checking across arbitrary design transformations. In ICCD, pp. 259-266, 2006.
    • (2006) ICCD , pp. 259-266
    • Baumgartner, J.1    Mony, H.2    Paruthi, V.3    Kanzelman, R.4    Janssen, G.5
  • 3
    • 33751411350 scopus 로고    scopus 로고
    • Automatic generalized phase abstraction for formal verification
    • P. Bjesse and J. Kukula. Automatic generalized phase abstraction for formal verification. In ICCAD, pp. 1076-1082, 2005.
    • (2005) ICCAD , pp. 1076-1082
    • Bjesse, P.1    Kukula, J.2
  • 4
    • 70350722613 scopus 로고    scopus 로고
    • Calypto Design Systems. Sequential Equivalence Checking: A new approach to functional verification of datapath and control logic changes. http://www.calypto.com/ wp-request.php?paper=sequential, 2007.
    • Calypto Design Systems. Sequential Equivalence Checking: A new approach to functional verification of datapath and control logic changes. http://www.calypto.com/ wp-request.php?paper=sequential, 2007.
  • 6
    • 0042134845 scopus 로고    scopus 로고
    • Behavioral consistency of C and Verilog programs using bounded model checking
    • E. M. Clarke, D. Kroening, and K. Yorav. Behavioral consistency of C and Verilog programs using bounded model checking. In DAC, pp. 368-371, 2003.
    • (2003) DAC , pp. 368-371
    • Clarke, E.M.1    Kroening, D.2    Yorav, K.3
  • 7
    • 51549097396 scopus 로고    scopus 로고
    • M. Haldar, G. Singh, S. Prabhakar, B. Dwivedi, and A. Ghosh. Construction of concrete verification models from C++. In DAC, pp. 942-947, 2008.
    • M. Haldar, G. Singh, S. Prabhakar, B. Dwivedi, and A. Ghosh. Construction of concrete verification models from C++. In DAC, pp. 942-947, 2008.
  • 8
    • 0034187246 scopus 로고    scopus 로고
    • AQUILA: An equivalence checking system for large sequential designs
    • S.-Y. Huang, K.-T. Cheng, K.-C. Chen, C.-Y. Huang, and F. Brewer. AQUILA: An equivalence checking system for large sequential designs. IEEE TOC, 49(5):443-464, 2000.
    • (2000) IEEE TOC , vol.49 , Issue.5 , pp. 443-464
    • Huang, S.-Y.1    Cheng, K.-T.2    Chen, K.-C.3    Huang, C.-Y.4    Brewer, F.5
  • 9
    • 47349130260 scopus 로고    scopus 로고
    • Industrial strength SAT-based alignability algorithm for hardware equivalence verification
    • D. Kaiss, M. Skaba, Z. Hanna, and Z. Khasidashvili. Industrial strength SAT-based alignability algorithm for hardware equivalence verification. In FMCAD, pp. 20-26, 2007.
    • (2007) FMCAD , pp. 20-26
    • Kaiss, D.1    Skaba, M.2    Hanna, Z.3    Khasidashvili, Z.4
  • 10
    • 34547492357 scopus 로고    scopus 로고
    • Post-reboot equivalence and compositional verification of hardware
    • Z. Khasidashvili, M. Skaba, D. Kaiss, and Z. Hanna. Post-reboot equivalence and compositional verification of hardware. In FMCAD, pp. 11-18, 2006.
    • (2006) FMCAD , pp. 11-18
    • Khasidashvili, Z.1    Skaba, M.2    Kaiss, D.3    Hanna, Z.4
  • 11
    • 34547248504 scopus 로고    scopus 로고
    • Memory modeling in ESL-RTL equivalence checking
    • A. Koelbl, J. R. Burch, and C. Pixley. Memory modeling in ESL-RTL equivalence checking. In DAC, pp. 205-209, 2007.
    • (2007) DAC , pp. 205-209
    • Koelbl, A.1    Burch, J.R.2    Pixley, C.3
  • 12
    • 16244364010 scopus 로고    scopus 로고
    • Dynamic transition relation simplification for bounded property checking
    • A. Kuehlmann. Dynamic transition relation simplification for bounded property checking. In ICCAD, pp. 50-57, 2004.
    • (2004) ICCAD , pp. 50-57
    • Kuehlmann, A.1
  • 13
    • 0036918496 scopus 로고    scopus 로고
    • Robust Boolean reasoning for equivalence checking and functional property verification
    • A. Kuehlmann, V. Paruthi, F. Krohm, and M. K. Ganai. Robust Boolean reasoning for equivalence checking and functional property verification. IEEE TCAD, 21:1377-1394, 2002.
    • (2002) IEEE TCAD , vol.21 , pp. 1377-1394
    • Kuehlmann, A.1    Paruthi, V.2    Krohm, F.3    Ganai, M.K.4
  • 14
    • 0003136457 scopus 로고    scopus 로고
    • Recent developments in high-level synthesis
    • Y.-L. Lin. Recent developments in high-level synthesis. ACM TODAES, 2(1):2-21, 1997.
    • (1997) ACM TODAES , vol.2 , Issue.1 , pp. 2-21
    • Lin, Y.-L.1
  • 15
    • 33846572844 scopus 로고    scopus 로고
    • th invariants and circuit sat solving
    • th invariants and circuit sat solving. In HLDVT, pp. 45-51, 2005.
    • (2005) HLDVT , pp. 45-51
    • Lu, F.1    Cheng, K.-T.2
  • 16
    • 57849147619 scopus 로고    scopus 로고
    • Scalable and scalably-verifiable sequential synthesis
    • A. Mishchenko, M. L. Case, R. K. Brayton, and S. Jang. Scalable and scalably-verifiable sequential synthesis. In ICCAD, 2008.
    • (2008) ICCAD
    • Mishchenko, A.1    Case, M.L.2    Brayton, R.K.3    Jang, S.4
  • 17
    • 84945924340 scopus 로고    scopus 로고
    • th GI-Conference, 104 of Theoretical Computer Science, pp. 167-183, Karlsruhe, 1981. Springer-Verlag.
    • th GI-Conference, volume 104 of Theoretical Computer Science, pp. 167-183, Karlsruhe, 1981. Springer-Verlag.
  • 18
    • 0000318151 scopus 로고
    • A theory and implementation of sequential hardware equivalence
    • C. Pixley. A theory and implementation of sequential hardware equivalence. IEEE TCAD, 11(12):1469-1478, 1992.
    • (1992) IEEE TCAD , vol.11 , Issue.12 , pp. 1469-1478
    • Pixley, C.1
  • 19
    • 0037984743 scopus 로고    scopus 로고
    • Sequential optimization in the absence of global reset
    • V. Singhal, C. Pixley, A. Aziz, S. Qadeer, and R. K. Brayton. Sequential optimization in the absence of global reset. ACM TODAES, 8(2):222-251, 2003.
    • (2003) ACM TODAES , vol.8 , Issue.2 , pp. 222-251
    • Singhal, V.1    Pixley, C.2    Aziz, A.3    Qadeer, S.4    Brayton, R.K.5
  • 20
    • 0034224829 scopus 로고    scopus 로고
    • Sequential equivalence checking based on structural similarities
    • C. A. J. van Eijk. Sequential equivalence checking based on structural similarities. IEEE TCAD, 19(7):814-819, 2000.
    • (2000) IEEE TCAD , vol.19 , Issue.7 , pp. 814-819
    • van Eijk, C.A.J.1
  • 21
    • 70350717294 scopus 로고    scopus 로고
    • Exploiting functional dependencies in finite state machine verification
    • C. A. J. van Eijk and J. A. G. Jess. Exploiting functional dependencies in finite state machine verification. In DATE, pp. 266-271, 1996.
    • (1996) DATE , pp. 266-271
    • van Eijk, C.A.J.1    Jess, J.A.G.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.