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Volumn 10, Issue 4, 2005, Pages 610-626

Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths

Author keywords

Behavior synthesis; Equivalence checking; Formal verification; High level synthesis

Indexed keywords


EID: 33745183745     PISSN: 10844309     EISSN: 10844309     Source Type: Journal    
DOI: 10.1145/1109118.1109121     Document Type: Conference Paper
Times cited : (21)

References (22)
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    • Behavioral consistency of C and Verilog programs using bounded model checking
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    • Formal verification of designs with complex control by symbolic simulation
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.