메뉴 건너뛰기




Volumn , Issue , 2012, Pages 279-289

Locality and utility co-optimization for practical capacity management of shared last level caches

Author keywords

Chip multiprocessors; Locality utility co optimization; Practical capacity management; Shared last level caches

Indexed keywords

ASSOCIATIVITY; CAPACITY MANAGEMENT; CHIP MULTIPROCESSOR; CO-OPTIMIZATION; EXPERIMENTAL OBSERVATION; INTERVAL PREDICTION; MAIN MEMORY; PERFORMANCE GAPS; PERFORMANCE IMPROVEMENTS; PROCESSING CORE; REPLACEMENT POLICY; SHARED LAST LEVEL CACHES; STORAGE COSTS; STORAGE OVERHEAD; THROUGHPUT IMPROVEMENT; UTILITY OPTIMIZATIONS;

EID: 84864031894     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2304576.2304615     Document Type: Conference Paper
Times cited : (12)

References (26)
  • 6
    • 34548042910 scopus 로고    scopus 로고
    • Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches
    • DOI 10.1109/MICRO.2006.49, 4041865, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-39
    • Moinuddin K. Qureshi and Yale N. Patt. Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches. In Proceedings of the 39th IEEE/ACM International Symposium on Microarchitecture, pages 423-432, December 2006. (Pubitemid 351337015)
    • (2006) Proceedings of the Annual International Symposium on Microarchitecture, MICRO , pp. 423-432
    • Qureshi, M.K.1    Patt, Y.N.2
  • 10
    • 35348920021 scopus 로고    scopus 로고
    • Adaptive insertion policies for high performance caching
    • DOI 10.1145/1250662.1250709, ISCA'07: 34th Annual International Symposium on Computer Architecture, Conference Proceedings
    • Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., and Joel Emer. Adaptive Insertion Policies for High Performance Caching. In Proceedings of the 34th International Symposium on Computer Architecture, pages 381-391, June 2007. (Pubitemid 47582119)
    • (2007) Proceedings - International Symposium on Computer Architecture , pp. 381-391
    • Qureshi, M.K.1    Jaleel, A.2    Patt, Y.N.3    Steely Jr., S.C.4    Emer, J.5
  • 13
    • 33846535493 scopus 로고    scopus 로고
    • The M5 simulator: Modeling networked systems
    • DOI 10.1109/MM.2006.82
    • Nathan L. Binkert, Ronald G. Dreslinski, Lisa R. Hsu, Kevin T. Lim, Ali G. Saidi, and Steven K. Reinhardt. The M5 Simulator: Modeling Networked Systems. IEEE Micro, 26(4):52-60, July 2006. (Pubitemid 46504889)
    • (2006) IEEE Micro , vol.26 , Issue.4 , pp. 52-60
    • Binkert, N.L.1    Dreslinski, R.G.2    Hsu, L.R.3    Lim, K.T.4    Saidi, A.G.5    Reinhardt, S.K.6
  • 14
    • 0031366315 scopus 로고    scopus 로고
    • Efficient hardware hashing functions for high performance computers
    • M. V. Ramakrishna, E. Fu, and E. Bahcekapili. Efficient Hardware Hashing Functions for High Performance Computers. IEEE Transactions on Computers, 46:1378-1381, December 1997. (Pubitemid 127760657)
    • (1997) IEEE Transactions on Computers , vol.46 , Issue.12 , pp. 1378-1381
    • Ramakrishna, M.V.1    Fu, E.2    Bahcekapili, E.3
  • 18
    • 0036949388 scopus 로고    scopus 로고
    • An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
    • DOI 10.1145/635508.605420
    • Changkyu Kim, Doug Burger, and Stephen W. Keckler. An Adaptive, Non-Uniform Cache Structure for Wire-Delay Dominated on-Chip Caches. In Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 211-222, March 2002. (Pubitemid 44892235)
    • (2002) Operating Systems Review (ACM) , vol.36 , Issue.5 , pp. 211-222
    • Kim, C.1    Burger, D.2    Keckler, S.W.3
  • 19
    • 27544495466 scopus 로고    scopus 로고
    • Victim replication: Maximizing capacity while hiding wire delay in tiled chip multiprocessors
    • Proceedings - 32nd International Symposium on Computer Architecture, ISCA 2005
    • Michael Zhang and Krste Asanovic. Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors. In Proceedings of the 32nd International Symposium on Computer Architecture, pages 336-345, June 2005. (Pubitemid 41543452)
    • (2005) Proceedings - International Symposium on Computer Architecture , pp. 336-345
    • Zhang, M.1    Asanovic, K.2
  • 20
    • 34548008288 scopus 로고    scopus 로고
    • ASR: Adaptive selective replication for CMP caches
    • DOI 10.1109/MICRO.2006.10, 4041867, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-39
    • Bradford M. Beckmann, Michael R. Marty, and David A. Wood. ASR: Adaptive Selective Replication for CMP Caches. In Proceedings of the 39th IEEE/ACM International Symposium on Microarchitecture, pages 443-454, Decebmer 2006. (Pubitemid 351337017)
    • (2006) Proceedings of the Annual International Symposium on Microarchitecture, MICRO , pp. 443-454
    • Beckmann, B.M.1    Marty, M.R.2    Wood, D.A.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.