Cache sharing management for performance fairness in chip multiprocessors

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2009, Pages 384-393

  Zhou, Xing ^a   Chen, Wenguang ^a   Zheng, Weimin ^a  

^a TSINGHUA UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MISS; CACHE SHARING; DATA-INTENSIVE APPLICATION; EXECUTION CYCLES; IN-CHIP; MANAGEMENT MECHANISMS; MISS-RATE; OFF-CHIP; PERFORMANCE IMPACT; RESOURCE SHARING; SHARED CACHE; SHARED RESOURCES;

BUFFER STORAGE; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; NANOTECHNOLOGY; PARALLEL ARCHITECTURES;

WEB SERVICES;

EID: 70449679127     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2009.40     Document Type: Conference Paper

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