Achieving non-inclusive cache performance with inclusive caches: Temporal Locality Aware (TLA) cache management policies

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2010, Pages 151-162

  Jaleel, Aamer ^a   Borch, Eric ^a   Bhandaru, Malini ^a   Steely Jr , Simon C ^a   Emer, Joel ^a,b  

^a INTEL CORPORATION   (United States)

^b MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Exclusion; Inclusion; Non inclusion; Replacement

Indexed keywords

CACHE CAPACITY; CACHE COHERENCE; CACHE HIERARCHIES; CACHE MANAGEMENT POLICIES; CACHE PERFORMANCE; EXCLUSION; HARDWARE STRUCTURES; INCLUSION PROPERTIES; NON-INCLUSION; REPLACEMENT; TEMPORAL LOCALITY;

EID: 79951719036     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2010.52     Document Type: Conference Paper

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