EPIMap: Using epimorphism to map applications on CGRAs

Proceedings - Design Automation Conference

Volumn , Issue , 2012, Pages 1284-1291

  Hamzeh, Mahdi ^a   Shrivastava, Aviral ^a   Vrudhula, Sarma ^a  

^a ARIZONA STATE UNIVERSITY   (United States)

Author keywords

coarse grained reconfigurable architectures; compilation; modulo scheduling

Indexed keywords

APPLICATION MAPPING; BENCHMARK PROGRAMS; COARSE GRAINED RECONFIGURABLE ARCHITECTURE; COMPILATION; MAPPING ALGORITHMS; MODULO SCHEDULING; POWER-EFFICIENCY; PROBLEM FORMULATION; RESOURCE LIMITATIONS; SEARCH SPACES;

COMPUTER AIDED DESIGN; CONFORMAL MAPPING; EMBEDDED SYSTEMS; PROGRAM COMPILERS;

BENCHMARKING;

EID: 84863558335     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2228360.2228600     Document Type: Conference Paper

References (26)

1. AA, T. V., RAGHAVAN, P., MAHLKE, S. A., SUTTER, B. D., SHRIVASTAVA, A., AND HANNIG, F. Compilation techniques for cgras: exploring all parallelization approaches. In CODES+ISSS (2010), pp. 185-186.
2. AHN, M., YOON, J., PAEK, Y., KIM, Y., KIEMB, M., AND CHOI, K. A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures. In Proc. DATE (2006), pp. 363-368.
3. BANSAL, N., GUPTA, S., DUTT, N., NICOLAU, A., AND GUPTA, R. Network topology exploration of mesh-based coarse-grain reconfigurable architectures. In Proc. DATE (2004), pp. 474-479.
4. BECKER, J., AND VORBACH, M. Architecture, memory and interface technology integration of an industrial/ academic configurable system-on-chip (csoc). In Proc. ISVLSI (2003), pp. 107-112.
5. BORKAR, S. Design challenges of technology scaling. IEEE Micro 19, 4 (1999), 23-29.
6. BOUWENS, F., BEREKOVIC, M., SUTTER, B. D., AND GAYDADJIEV, G. Architecture enhancements for the adres coarse-grained reconfigurable array. In Proc. HiPEAC (2008), pp. 66-81.
7. CHEN, D. C. Programmable arithmetic devices for high speed digital signal processing. PhD thesis, University of California, Berkeley, 1992.
8. DIMITROULAKOS, G., GALANIS, M., AND GOUTIS, C. Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures. In Proc. IPDPS (2006), pp. 113-122.
9. FRIEDMAN, S., CARROLL, A., VAN ESSEN, B., YLVISAKER, B., EBELING, C., AND HAUCK, S. Spr: an architecture-adaptive cgra mapping tool. In Proc. FPGA (2009), pp. 191-200.
10. GAREY, M. R., AND JOHNSON, D. S. Computers and Intractability: A Guide to the Theory of NP-Completeness. W. H. Freeman & Co., New York, NY, USA, 1979.
11. GOLDSTEIN, S., SCHMIT, H., MOE, M., BUDIU, M., CADAMBI, S., TAYLOR, R., AND LAUFER, R. Piperench: a coprocessor for streaming multimedia acceleration. In Proc. ISCA (1999), pp. 28 -39.
12. GUO, Y., HOEDE, C., AND SMIT, G. A pattern selection algorithm for multi-pattern scheduling. In Proc. PDPTA (2006), pp. 198-205.
13. HARTENSTEIN, R. A decade of reconfigurable computing: a visionary retrospective. In Proc. DATE (2001), pp. 642-649.
14. HARTENSTEIN, R., AND KRESS, R. A datapath synthesis system for the reconfigurable datapath architecture. In Proc. ASP-DAC (1995), pp. 479-484.
15. HATANAKA, A., AND BAGHERZADEH, N. A modulo scheduling algorithm for a coarse-grain reconfigurable array template. In Proc. IPDPS (2007), pp. 1-8.
16. HELL, P., AND NESETRIL, J. Graphs and Homomorphisms. Oxford University Press, New York, NY, USA, 2004.
17. LEE, J.-E., CHOI, K., AND DUTT, N. D. Compilation approach for coarse-grained reconfigurable architectures. IEEE Design and Test of Computers 20, 1 (2003), 26-33.
18. LEE, M.-H., SINGH, H., LU, G., BAGHERZADEH, N., KURDAHI, F. J., FILHO, E. M. C., AND ALVES, V. C. Design and implementation of the morphosys reconfigurable computingprocessor. J. VLSI Signal Process. Syst. 24 (2000), 147-164.
19. LEVI, G. A note on the derivation of maximal common subgraphs of two directed or undirected graphs. Calcolo 9 (Dec. 1973), 341-352.
20. MEI, B., VERNALDE, S., VERKEST, D., AND LAUWEREINS, R. Design methodology for a tightly coupled vliw/reconfigurable matrix architecture: a case study. In Proc. DATE (2004), pp. 1224-1229.
21. MIRSKY, E., AND DEHON, A. Matrix: a reconfigurable computing architecture with configurable instruction distribution and deployable resources. In Proc. FPGAs for Custom Computing Machines (1996), pp. 157-166.
22. MIYAMORI, T., AND OLUKOTUN, K. Remarc: Reconfigurable multimedia array coprocessor. IEICE Trans. on Information and Systems (1998), 389-397.
23. PARK, H., FAN, K., MAHLKE, S. A., OH, T., KIM, H., AND KIM, H.-S. Edge-centric modulo scheduling for coarse-grained reconfigurable architectures. In Proc. PACT (2008), pp. 166-176.
24. RAU, B. R. Iterative modulo scheduling: an algorithm for software pipelining loops. In Proc. MICRO (1994), pp. 63-74.
25. WOH, M., MAHLKE, S., MUDGE, T., AND CHAKRABARTI, C. Mobile supercomputers for the next-generation cell phone. Computer 43, 1 (2010), 81-85.
26. YOON, J., SHRIVASTAVA, A., PARK, S., AHN, M., AND PAEK, Y. A graph drawing based spatial mapping algorithm for coarse-grained reconfigurable architectures. IEEE Trans. on VLSI Systems 17, 11 (2009), 1565-1578.