Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures

20th International Parallel and Distributed Processing Symposium, IPDPS 2006

Volumn 2006, Issue , 2006, Pages

  Dimitroulakos, Gregory ^a   Galanis, Michails D ^a   Goutis, Costas E ^a  

^a UNIVERSITY OF PATRAS   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CACHE MEMORY; COMPUTER SCIENCE; FILE ORGANIZATION; LOGIC DESIGN; OPTIMIZATION;

CACHING MEMORY DATA; MAPPING ALGORITHMS; MODULO SCHEDULING TECHNIQUE; OPERATION PARALLELISM;

PROGRAM COMPILERS;

EID: 33847205022     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2006.1639349     Document Type: Conference Paper

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