Architecture enhancements for the ADRES coarse-grained reconfigurable array

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 4917 LNCS, Issue , 2008, Pages 66-81

  Bouwens, Frank ^a,b   Berekovic, Mladen ^a,b   De Sutter, Bjorn ^a   Gaydadjiev, Georgi ^b  

^a IMEC   (Belgium)

^b DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE; COMMERCE; HIGH PERFORMANCE LIQUID CHROMATOGRAPHY; OPTIMIZATION; POWER GENERATION; TOPOLOGY;

2-D ARRAY; 90 NM TECHNOLOGY; CLOCK GATING; COARSE-GRAINED; DESIGN SPACES; EMBEDDED ARCHITECTURES; EMBEDDED MULTIMEDIA; ENERGY DELAY; FUNCTIONAL UNITS; INTERCONNECTION TOPOLOGIES; INTERNATIONAL CONFERENCES; OPTIMIZED ARCHITECTURES; PERFORMANCE TRADE-OFFS; POWER EFFICIENCIES; RE-CONFIGURABLE; RE-CONFIGURABLE ARCHITECTURE; RECONFIGURABLE ARRAYS; REGISTER FILES; SPECIFIC HARDWARE;

PROGRAM COMPILERS;

EID: 49949099734     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-77560-7_6     Document Type: Conference Paper

References (12)

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