Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI

Proceedings - Design Automation Conference

Volumn , Issue , 2012, Pages 398-405

  Park, Sunghyun ^a   Krishna, Tushar ^a   Chen, Chia Hsin ^a   Daya, Bhavya ^a   Chandrakasan, Anantha ^a   Peh, Li Shiuan ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

chip prototype; low swing signaling; multicast optimization; network on chip; theoretical mesh limits; virtual bypassing

Indexed keywords

CHIP PROTOTYPES; LOW-SWING SIGNALING; MULTICAST OPTIMIZATION; NETWORK ON CHIP; THEORETICAL MESH LIMITS; VIRTUAL BYPASSING;

COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; MULTICASTING; OPTIMIZATION; RESEARCH; VLSI CIRCUITS;

ROUTERS;

EID: 84863551686     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2228360.2228431     Document Type: Conference Paper

References (24)

1. I. Arsovski and R. Wistort. Self-referenced sense amplifier for across-chipvariation immune sensing in high-performance content-addressable memories. In IEEE Custom Integrated Circuits Conf., pages 453-456, 2006.
2. S. Bell et al. A 118.4 gb/s multi-casting network-on-chip with hierarchical star-ring combined topology for real-time object recognition. IEEE Journal of Solid-State Circuits, 45:1399-1409, 2010.
3. C.-H. O. Chen et al. Physical vs. virtual express topologies with low-swing links for future many-core nocs. In Int'l Symp. on Networks-on-Chip, May 2010.
4. M. Coppola et al. Spidergon: a novel on-chip communication network. In Int'l Symp. on System-on-Chip, page 15, 2004.
5. W. J. Dally and B. Towles. Route packets not wires: On-chip interconnection networks. In DAC, June 2001.
6. W. J. Dally and B. Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers, 2004.
7. P. Gratz et al. On-chip interconnection networks of the trips chip. IEEE Micro, 27(5):41-50, 2007.
8. S. Heo and K. Asanovic. Replacing global wires with an on-chip network: A power analysis. In Int'l Symp. on Low Power Elect. and Design, pages 369-374, 2005.
9. R. Ho et al. High-speed and low-energy capacitive-driven on-chip wires. In Int'l Solid-State Circuits Conf., pages 412-413, 2007.
10. Y. Hoskote et al. A 5-ghz mesh interconect for a teraflops processor. IEEE Micro, 27(5):51-61, 2007.
11. J. Howard et al. A 48-core ia-32 message-passing processor with dvfs in 45nm cmos. In Int'l Solid-State Circuits Conf., pages 108-109, 2010.
12. A. Kahng et al. Orion 2.0: A fast and accurate noc power and area model for early-stage design space exploration. In Proc. Design, Automation and Test in Europe, pages 423-428, 2009.
13. B. Kim and V. Stojanovic. A 4gb/s/ch 356fj/b 10mm equalized on-chip interconnect with nonlinear charge-injecting transmit filter and transimpedance receiver in 90nm cmos. In Int'l Solid-State Circuits Conf., pages 66-67, 2009.
14. T. Krishna et al. Swift: A swing-reduced interconnect for a token-based network-on-chip in 90nm cmos. In Int'l Conf. on Computer Design, pages 439-446, 2010.
15. T. Krishna et al. Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication. In MICRO, Dec 2011.
16. A. Kumar et al. Express virtual channels: Towards the ideal interconnection fabric. In Int'l Symp. on Computer Architecture, June 2007.
17. A. Kumar et al. Token flow control. In MICRO, Nov 2008.
18. E. Mensink et al. A 0.28pj/b 2gb/s/ch transceiver in 90nm cmos for 10mm on-chip interconnects. In Int'l Solid-State Circuits Conf., pages 314-315, 2000.
19. M. Qazi et al. A 512kb 8t sram macro operating down to 0.57v with an ac-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm soi cmos. In Int'l Solid-State Circuits Conf., pages 350-351, 2010.
20. J. M. Rabaey et al. Digital Integrated Circuits: A design perspective. Prentice Hall, 2nd Edition, 1998.
21. M. B. Taylor et al. The raw microprocessor: A computational fabric for software circuits and general-purpose programs. IEEE Micro, 22(2):25-35, 2002.
22. N. Verma and A. P. Chandrakasan. A high-density 45nm sram using small-signal non-strobed regenerative sensing. In Int'l Solid-State Circuits Conf., pages 380-381, 2008.
23. D. Wentzlaff et al. On-chip interconnection architecture of the tile processor. IEEE Micro, 27(5):15-31, 2007.
24. H. Zhang et al. A 1 v heterogeneous reconfigurable processor ic for baseband wireless applications. In Int'l Solid-State Circuits Conf., pages 68-69, 2000.